System and method for task queue management of virtual devices using a plurality of processors
    1.
    发明申请
    System and method for task queue management of virtual devices using a plurality of processors 失效
    使用多个处理器的虚拟设备的任务队列管理的系统和方法

    公开(公告)号:US20050081202A1

    公开(公告)日:2005-04-14

    申请号:US10670838

    申请日:2003-09-25

    IPC分类号: G06F9/46

    CPC分类号: G06F9/505

    摘要: A task queue manager manages the task queues corresponding to virtual devices. When a virtual device function is requested, the task queue manager determines whether an SPU is currently assigned to the virtual device task. If an SPU is already assigned, the request is queued in a task queue being read by the SPU. If an SPU has not been assigned, the task queue manager assigns one of the SPUs to the task queue. The queue manager assigns the task based upon which SPU is least busy as well as whether one of the SPUs recently performed the virtual device function. If an SPU recently performed the virtual device function, it is more likely that the code used to perform the function is still in the SPU's local memory and will not have to be retrieved from shared common memory using DMA operations.

    摘要翻译: 任务队列管理器管理与虚拟设备相对应的任务队列。 当请求虚拟设备功能时,任务队列管理器确定SPU当前是否被分配给虚拟设备任务。 如果已经分配了SPU,则该请求在SPU所读取的任务队列中排队。 如果尚未分配SPU,则任务队列管理器将其中一个SPU分配给任务队列。 队列管理器根据哪个SPU最不忙,以及一个SPU最近是否执行了虚拟设备功能来分配任务。 如果SPU最近执行了虚拟设备功能,则用于执行该功能的代码更有可能仍在SPU的本地存储器中,并且不需要使用DMA操作从共享的公共存储器中检索。

    System and method for virtual devices using a plurality of processors
    2.
    发明申请
    System and method for virtual devices using a plurality of processors 失效
    使用多个处理器的虚拟设备的系统和方法

    公开(公告)号:US20050071526A1

    公开(公告)日:2005-03-31

    申请号:US10670835

    申请日:2003-09-25

    CPC分类号: G06F9/4843 G06F9/544

    摘要: A system and method is provided to allow virtual devices that use a plurality of processors in a multiprocessor systems, such as the BE environment. Using this method, a synergistic processing unit (SPU) can either be dedicated to performing a particular function (i.e., audio, video, etc.) or a single SPU can be programmed to perform several functions on behalf of the other processors in the system. The application, preferably running in one of the primary (PU) processors, issues IOCTL commands through device drivers that correspond to SPUs. The kernel managing the primary processors responds by sending an appropriate message to the SPU that is performing the dedicated function. Using this method, an SPU can be virtualized for swapping multiple tasks or dedicated to performing a particular task.

    摘要翻译: 提供了一种系统和方法,以允许在诸如BE环境的多处理器系统中使用多个处理器的虚拟设备。 使用这种方法,协同处理单元(SPU)可以专用于执行特定功能(即,音频,视频等),或者单个SPU可被编程为代表系统中的其他处理器执行若干功能 。 优选地,在主(PU)处理器之一中运行的应用通过对应于SPU的设备驱动器发出IOCTL命令。 管理主处理器的内核通过向执行专用功能的SPU发送适当的消息来做出响应。 使用此方法,可以将SPU虚拟化用于交换多个任务或专用于执行特定任务。

    Destructive DMA lists
    3.
    发明申请
    Destructive DMA lists 失效
    破坏性DMA列表

    公开(公告)号:US20070088866A1

    公开(公告)日:2007-04-19

    申请号:US11252532

    申请日:2005-10-18

    IPC分类号: G06F13/28

    CPC分类号: G06F13/28

    摘要: A buffer, a method, and a computer program product for DMA transfers are provided that are designed to save memory space within a local memory of a processor. The buffer is a return buffer with a portion reserved for DMA lists. A DMA controller accomplishes DMA transfers by: reading address elements from a DMA list located in the DMA list portion; reading the corresponding data from system memory; and copying the corresponding data to the return buffer portion. This buffer saves space because when the buffer begins to fill up the corresponding return data can overwrite the data in the DMA list. Accordingly, the DMA list overlays on top of the return buffer, such that the return data can destruct the DMA list and the extra storage space for the DMA list is saved.

    摘要翻译: 提供了用于DMA传输的缓冲器,方法和计算机程序产品,其被设计为在处理器的本地存储器内节省存储器空间。 缓冲区是具有为DMA列表保留的部分的返回缓冲区。 DMA控制器通过以下方式完成DMA传输:从位于DMA列表部分的DMA列表读取地址元素; 从系统内存读取相应的数据; 并将相应的数据复制到返回缓冲器部分。 此缓冲区可节省空间,因为当缓冲区开始填满相应的返回数据时,可以覆盖DMA列表中的数据。 因此,DMA列表覆盖在返回缓冲器的顶部,使得返回数据可以破坏DMA列表,并且保存DMA列表的额外的存储空间。

    Method for broadcasting a condition to threads executing on a plurality of on-chip processors
    4.
    发明申请
    Method for broadcasting a condition to threads executing on a plurality of on-chip processors 有权
    用于向多个片上处理器执行的线程广播条件的方法

    公开(公告)号:US20060085791A1

    公开(公告)日:2006-04-20

    申请号:US10965634

    申请日:2004-10-14

    IPC分类号: G06F9/46

    CPC分类号: G06F9/542 G06F2209/544

    摘要: The present invention provides for notifying threads. A determination is made whether there is a condition for which a thread is to be notified. If so, a notification indicia is broadcasted. A flag is set in at least one memory storage area as a function of the notification indicia wherein the setting the flag occurs without the intervention of an operating system. Therefore, latencies for notification of threads are minimized.

    摘要翻译: 本发明提供通知线程。 确定是否存在要通知线程的条件。 如果是,广播通知标记。 作为通知标记的功能的至少一个存储器存储区域中设置标志,其中在没有操作系统的干预的情况下发生标志。 因此,线程通知的延迟最小化。

    System and method for virtualization of processor resources
    5.
    发明申请
    System and method for virtualization of processor resources 有权
    处理器资源虚拟化的系统和方法

    公开(公告)号:US20060069878A1

    公开(公告)日:2006-03-30

    申请号:US10955093

    申请日:2004-09-30

    IPC分类号: G06F12/08 G06F12/00

    摘要: A system and method for virtualization of processor resources is presented. A thread is created on a processor and the processor's local memory is mapped into an effective address space. In doing so, the processor's local memory is accessible by other processors, regardless of whether the processor is running. Additional threads create additional local memory mappings into the effective address space. The effective address space corresponds to either a physical local memory or a “soft” copy area. When the processor is running, a different processor may access data that is located in the first processor's local memory from the processor's local storage area. When the processor is not running, a softcopy of the processor's local memory is stored in a memory location (i.e. locked cache memory, pinned system memory, virtual memory, etc.) for other processors to continue accessing.

    摘要翻译: 提出了一种用于处理器资源虚拟化的系统和方法。 在处理器上创建线程,并将处理器的本地内存映射到有效的地址空间。 这样做,处理器的本地内存可以由其他处理器访问,无论处理器是否正在运行。 附加线程会在有效地址空间中创建额外的本地内存映射。 有效地址空间对应于物理本地存储器或“软”复制区域。 当处理器运行时,不同的处理器可以从处理器的本地存储区域访问位于第一处理器的本地存储器中的数据。 当处理器未运行时,处理器的本地存储器的软拷贝存储在其他处理器的存储器位置(即锁定的高速缓冲存储器,固定的系统存储器,虚拟存储器等)中以继续访问。

    Light weight context switching technique
    6.
    发明申请
    Light weight context switching technique 失效
    轻量级上下文切换技术

    公开(公告)号:US20060015876A1

    公开(公告)日:2006-01-19

    申请号:US10891773

    申请日:2004-07-15

    IPC分类号: G06F9/46

    CPC分类号: G06F9/461 G06F9/485

    摘要: An apparatus, a method, and a computer program product are provided for more efficiently allowing context switching. Currently, context switching can be costly because of both memory requirements to store data from pre-empted applications, as well as the bus requirements to move the data at pre-emption. To alleviate at least some of the costs associated with context switching, addition fields, either with associated Application Program Interfaces (APIs) or coupled to application modules, can be employed to indicate points of light weight context during the operation of an application. Therefore, an operating system can pre-empt applications at points where the context is relatively light, reducing the costs on both storage and on bus usage.

    摘要翻译: 提供了一种用于更有效地允许上下文切换的装置,方法和计算机程序产品。 目前,上下文切换可能是昂贵的,因为存储器要求存储来自抢占应用的数据,以及总线要求以优先移动数据。 为了减轻与上下文切换相关联的至少一些成本,可以使用具有相关联的应用程序接口(API)或耦合到应用模块的附加字段来在应用的操作期间指示轻量级上下文的点。 因此,操作系统可以在上下文相对较轻的点预占应用程序,从而降低存储和总线使用的成本。

    System and method for asymmetric heterogeneous multi-threaded operating system
    7.
    发明申请
    System and method for asymmetric heterogeneous multi-threaded operating system 失效
    非对称异构多线程操作系统和方法

    公开(公告)号:US20050081203A1

    公开(公告)日:2005-04-14

    申请号:US10670841

    申请日:2003-09-25

    IPC分类号: G06F9/46

    CPC分类号: G06F9/4881

    摘要: A system and method for an asymmetric heterogeneous multi-threaded operating system are presented. A processing unit (PU) provides a trusted mode environment in which an operating system executes. A heterogeneous processor environment includes a synergistic processing unit (SPU) that does not provide trusted mode capabilities. The PU operating system uses two separate and distinct schedulers which are a PU scheduler and an SPU scheduler to schedule tasks on a PU and an SPU, respectively. In one embodiment, the heterogeneous processor environment includes a plurality of SPUs. In this embodiment, the SPU scheduler may use a single SPU run queue to schedule tasks for the plurality of SPUs or, the SPU scheduler may use a plurality of run queues to schedule SPU tasks whereby each of the run queues correspond to a particular SPU.

    摘要翻译: 提出了一种用于非对称异构多线程操作系统的系统和方法。 处理单元(PU)提供操作系统执行的信任模式环境。 异构处理器环境包括不提供可信模式能力的协同处理单元(SPU)。 PU操作系统使用两个独立和不同的调度器,PU调度器和SPU调度器分别在PU和SPU上调度任务。 在一个实施例中,异构处理器环境包括多个SPU。 在本实施例中,SPU调度器可以使用单个SPU运行队列来调度多个SPU的任务,或者SPU调度器可以使用多个运行队列调度SPU任务,由此每个运行队列对应于特定SPU。

    System and method for loading software on a plurality of processors
    8.
    发明申请
    System and method for loading software on a plurality of processors 失效
    用于在多个处理器上加载软件的系统和方法

    公开(公告)号:US20050086655A1

    公开(公告)日:2005-04-21

    申请号:US10670842

    申请日:2003-09-25

    CPC分类号: G06F9/44557 G06F9/44526

    摘要: A system and method for loading software on a plurality of processors is presented. A processing unit (PU) retrieves a file from system memory and loads it into its internal memory. The PU extracts a processor type from the file's header which identifies whether the file should execute on the PU or a synergistic processing unit (SPU). If an SPU should execute the file, the PU DMA's the file to the SPU for execution. In one embodiment, the file is a combined file which includes both PU and SPU code. In this embodiment, the PU identifies one or more section headers included in the file which indicates embedded SPU code within the combined file. In this embodiment, the PU extracts the SPU code from the combined file and DMA's the extracted code to an SPU for execution.

    摘要翻译: 提出了一种用于在多个处理器上加载软件的系统和方法。 处理单元(PU)从系统存储器检索文件并将其加载到其内部存储器中。 PU从文件头中提取一种处理器类型,用于标识文件是否应在PU或协同处理单元(SPU)上执行。 如果SPU应该执行该文件,PU DMA将该文件提交给SPU执行。 在一个实施例中,该文件是包括PU和SPU代码的组合文件。 在该实施例中,PU识别包括在文件中的一个或多个区段标题,其指示组合文件内的嵌入式SPU代码。 在本实施例中,PU从组合文件中提取SPU代码,并将提取的代码DMA提取给SPU以执行。

    System and method for sharing resources between real-time and virtualizing operating systems
    9.
    发明申请
    System and method for sharing resources between real-time and virtualizing operating systems 审中-公开
    在实时和虚拟化操作系统之间共享资源的系统和方法

    公开(公告)号:US20060070069A1

    公开(公告)日:2006-03-30

    申请号:US10955184

    申请日:2004-09-30

    IPC分类号: G06F9/46

    CPC分类号: G06F9/5016 G06F9/544

    摘要: A system and method for sharing resources between real-time and virtualizing operating systems is presented. A computer system uses effective address mapping of support processors' local memory to share resources between separate operating systems. When threads are created for either operating system, the thread's corresponding processor memory is mapped into an effective address space. In doing so, the processor's local memory is accessible by the thread, regardless of whether the processor is running, or whether the processor is executing a different thread from a different operating system. For example, a computer system may have eight support processors and running two operating systems whereby the first operating system requires six support processors and the second operating system requires all eight support processors. In this example, resources are virtualized and shared between the two operating systems in order to meet the requirements of both operating systems.

    摘要翻译: 介绍了一种在实时和虚拟化操作系统之间共享资源的系统和方法。 计算机系统使用支持处理器的本地存储器的有效地址映射来在不同的操作系统之间共享资源。 当为任一操作系统创建线程时,线程的相应处理器内存映射到有效的地址空间。 在这样做时,处理器的本地内存可由线程访问,无论处理器是否在运行,还是处理器是否正在从不同的操作系统执行不同的线程。 例如,计算机系统可以具有八个支持处理器并且运行两个操作系统,由此第一操作系统需要六个支持处理器,而第二操作系统需要所有八个支持处理器。 在这个例子中,为了满足两个操作系统的要求,在两个操作系统之间虚拟化和共享资源。

    System and method for asynchronous linked data structure traversal
    10.
    发明申请
    System and method for asynchronous linked data structure traversal 有权
    用于异步链接数据结构遍历的系统和方法

    公开(公告)号:US20070043746A1

    公开(公告)日:2007-02-22

    申请号:US11204415

    申请日:2005-08-16

    IPC分类号: G06F7/00

    摘要: A system and method for asynchronously traversing a disjoint linked data structure is presented. A synergistic processing unit (SPU) includes a handler that works in conjunction with a memory flow controller (MFC) to traverse a disjoint linked data structure. The handler compares a search value with a node value, and provides the MFC with an effective address of the next node to traverse based upon the comparison. In turn, the MFC retrieves the corresponding node data from system memory and stores the node data in the SPU's local storage area. The MFC stalls processing and sends an asynchronous event interrupt to the SPU which, as a result, instructs the handler to retrieve and compare the latest node data in the local storage area with the search value. The traversal continues until the handler matches the search value with a node value or until the handler determines a failed search.

    摘要翻译: 提出了一种用于异步遍历不相交的数据结构的系统和方法。 协同处理单元(SPU)包括与存储器流控制器(MFC)一起工作的处理程序,以遍历不相交的数据结构。 处理程序将搜索值与节点值进行比较,并根据比较为MFC提供下一个节点的有效地址进行遍历。 反过来,MFC从系统存储器检索相应的节点数据,并将节点数据存储在SPU的本地存储区域中。 MFC停止处理并向SPU发送异步事件中断,结果指示处理程序检索和比较本地存储区域中的最新节点数据与搜索值。 遍历继续,直到处理程序与搜索值与节点值匹配,或者直到处理程序确定失败的搜索。