System and method for DMA controller with multi-dimensional line-walking functionality
    1.
    发明申请
    System and method for DMA controller with multi-dimensional line-walking functionality 有权
    具有多维行走功能的DMA控制器的系统和方法

    公开(公告)号:US20060047864A1

    公开(公告)日:2006-03-02

    申请号:US10926589

    申请日:2004-08-26

    IPC分类号: G06F13/28

    CPC分类号: G06F13/28

    摘要: A system and method for a DMA controller with multi-dimensional line-walking functionality is presented. A processor includes an intelligent DMA controller, which loads a line description that corresponds to a shape or line. The intelligent DMA controller moves through a memory map and retrieves data based upon the line description that includes a major step and a minor step. In turn, the intelligent DMA controller retrieves data from the shared memory without assistance from its corresponding processor. In one embodiment, the intelligent DMA controller may analyze a line using the rate of change along its minor axes in conjunction with locations where the line intersects subspaces and store array spans of contiguous memory along the line's major axis.

    摘要翻译: 提出了一种具有多维行走功能的DMA控制器的系统和方法。 处理器包括智能DMA控制器,其加载对应于形状或线的线描述。 智能DMA控制器通过存储器映射移动,并根据包括主要步骤和次要步骤的行描述检索数据。 反过来,智能DMA控制器从共享存储器中检索数据,而不需要相应处理器的帮助。 在一个实施例中,智能DMA控制器可以使用沿着其次轴的变化速率与线与线路相交的位置并沿着线的长轴存储连续存储器的阵列跨度来分析线。

    System and method for encrypting and verifying messages using three-phase encryption
    2.
    发明申请
    System and method for encrypting and verifying messages using three-phase encryption 失效
    使用三相加密加密和验证消息的系统和方法

    公开(公告)号:US20050008162A1

    公开(公告)日:2005-01-13

    申请号:US10464891

    申请日:2003-06-19

    IPC分类号: H04L9/06 H04L9/00

    摘要: A method and system for encrypting and verifying the integrity of a message using a three-phase encryption process is provided. A source having a secret master key that is shared with a target receives the message and generates a random number. The source then generates: a first set of intermediate values from the message and the random number; a second set of intermediate values from the first set of values; and a cipher text from the second set of values. At the three phases, the values are generated using the encryption function of a block cipher encryption/decryption algorithm. The random number and the cipher text are transmitted to the target, which decrypts the cipher text by reversing the encryption process. The target verifies the integrity of the message by comparing the received random number with the random number extracted from the decrypted cipher text.

    摘要翻译: 提供了使用三相加密处理来加密和验证消息的完整性的方法和系统。 具有与目标共享的秘密主密钥的源接收消息并生成随机数。 然后,源产生:来自消息和随机数的第一组中间值; 来自第一组值的第二组中间值; 和来自第二组值的密文。 在三个阶段,使用块密码加密/解密算法的加密功能生成这些值。 随机数和密文被发送到目标,通过反转加密过程来解密密文。 目标通过将接收到的随机数与从解密的密文提取的随机数进行比较来验证消息的完整性。

    APPARATUS AND METHOD FOR ENSURING MAXIMUM CODE MOTION OF ACCESSES TO DMA BUFFERS
    3.
    发明申请
    APPARATUS AND METHOD FOR ENSURING MAXIMUM CODE MOTION OF ACCESSES TO DMA BUFFERS 失效
    用于确保DMA缓存访问的最大代码运动的装置和方法

    公开(公告)号:US20070240142A1

    公开(公告)日:2007-10-11

    申请号:US11278759

    申请日:2006-04-05

    IPC分类号: G06F9/45

    CPC分类号: G06F8/4441

    摘要: A “kill” intrinsic that may be used in programs for designating specific data objects as having been “killed” by a preceding action is provided. The concept of a data object being “killed” is that the compiler is informed that no operations (e.g., loads and stores) on that data object, or its aliases, can be moved across the point in the program flow where the data object is designated as having been “killed.” The “kill” intrinsic limits the reordering capability of an optimization scheduler of a compiler with regard to operations performed on “killed” data objects. The “kill” intrinsic may be used with DMA operations. Data objects being DMA'ed from a local store of a processor may be “killed” through use of the “kill” intrinsic prior to submitting the DMA request. Data objects being DMA'ed to the local store of the processor may be “killed” after verifying the transfer completes.

    摘要翻译: 提供了可以用于将特定数据对象指定为被前面的动作“杀死”的程序中的“杀死”内在的。 数据对象被“杀死”的概念是,通知编译器不会将数据对象或其别名上的任何操作(例如,加载和存储)移动到程序流中的数据对象的位置 被指定为“被杀死”。 “杀死”内在因素限制了编译器针对“已杀死”数据对象执行的操作的优化调度程序的重新排序能力。 “kill”内在函数可用于DMA操作。 从处理器的本地存储器DMA进行DMA的数据对象可能在提交DMA请求之前通过使用“kill”内在的“死机”。 在验证传输完成之后,DMA处理器的本地存储器的数据对象可能被“杀死”。

    EFFICIENT TRIANGULAR SHAPED MESHES
    4.
    发明申请
    EFFICIENT TRIANGULAR SHAPED MESHES 审中-公开
    高效三角形网格

    公开(公告)号:US20070188487A1

    公开(公告)日:2007-08-16

    申请号:US11548242

    申请日:2006-10-10

    IPC分类号: G06T15/00

    CPC分类号: G06T17/20 G06T15/00

    摘要: The present invention renders a triangular mesh for employment in graphical displays. The triangular mesh comprises triangle-shaped graphics primitives. The triangle-shaped graphics primitives represent a subdivided triangular shape. Each triangle-shaped graphics primitive shares defined vertices with adjoining triangle-shaped graphics primitives. These shared vertices are transmitted and employed for the rendering of the triangle-shaped graphics primitives.

    摘要翻译: 本发明使图形显示器中使用三角形网格。 三角形网格包含三角形图形图元。 三角形图形图元表示细分的三角形形状。 每个三角形图形基元与相邻的三角形图形基元共享定义的顶点。 这些共享顶点被传送并用于渲染三角形图形基元。

    Apparatus and method for performing externally assisted calls in a heterogeneous processing complex
    5.
    发明申请
    Apparatus and method for performing externally assisted calls in a heterogeneous processing complex 失效
    在异构处理复合体中执行外部辅助呼叫的装置和方法

    公开(公告)号:US20070104204A1

    公开(公告)日:2007-05-10

    申请号:US11269290

    申请日:2005-11-08

    IPC分类号: H04L12/56

    CPC分类号: G06F9/547

    摘要: An apparatus and method are provided for accessing, by an application running on a first processor, operating system services from an operating system running on a second processor by performing an assisted call. A data plane processor first constructs a parameter area based on the input and output parameters for the function that requires control processor assistance. The current values for the input parameters are copied into the parameter area. An assisted call message is generated based on a combination of a pointer to the parameter area and a specific library function opcode for the library function that is being called. The assisted call message is placed into the processor's stack immediately following a stop-and-signal instruction. The control plane processor is signaled to perform the library function corresponding to the opcode on behalf of the data plane processor by executing a stop and signal instruction.

    摘要翻译: 提供了一种装置和方法,用于通过执行辅助呼叫从运行在第一处理器上的应用程序访问来自在第二处理器上运行的操作系统的操作系统服务。 数据平面处理器首先根据需要控制处理器辅助的功能的输入和输出参数来构建参数区域。 输入参数的当前值被复制到参数区域。 基于指向参数区域的指针和正被调用的库函数的特定库函数操作码的组合,生成辅助呼叫消息。 辅助呼叫消息在紧跟停止信号指令之后立即放入处理器的堆栈中。 通过执行停止和信号指令,用信号通知控制平面处理器代表数据平面处理器执行对应于操作码的库功能。

    System and method for partitioning processor resources based on memory usage
    6.
    发明申请
    System and method for partitioning processor resources based on memory usage 失效
    基于内存使用分配处理器资源的系统和方法

    公开(公告)号:US20060095901A1

    公开(公告)日:2006-05-04

    申请号:US11050020

    申请日:2005-02-03

    IPC分类号: G06F9/45

    摘要: A system and method for partitioning processor resources based on memory usage is provided. A compiler determines the extent to which a process is memory-bound and accordingly divides the process into a number of threads. When a first thread encounters a prolonged instruction, the compiler inserts a conditional branch to a second thread. When the second thread encounters a prolonged instruction, a conditional branch to a third thread is executed. This continues until the last thread conditionally branches back to the first thread. An indirect segmented register file is used so that the “return to” and “branch to” logical registers within each thread are the same (e.g., R1 and R2) for each thread. These logical registers are mapped to hardware registers that store actual addresses. The indirect mapping is altered to bypass completed threads. When the last thread completes it may signal an external process.

    摘要翻译: 提供了一种基于内存使用来分配处理器资源的系统和方法。 编译器确定进程是内存限制的程度,从而将进程划分为多个线程。 当第一个线程遇到延长的指令时,编译器将条件分支插入第二个线程。 当第二个线程遇到延长的指令时,执行到第三个线程的条件分支。 这将持续到最后一个线程有条件地分支回到第一个线程。 使用间接分段寄存器文件,使得每个线程内的“返回”和“分支到”逻辑寄存器对于每个线程是相同的(例如,R 1和R 2)。 这些逻辑寄存器映射到存储实际地址的硬件寄存器。 间接映射被更改为绕过完成的线程。 当最后一个线程完成时,它可能会发出外部进程信号。

    System and method for hiding memory latency
    7.
    发明申请
    System and method for hiding memory latency 审中-公开
    隐藏内存延迟的系统和方法

    公开(公告)号:US20060080661A1

    公开(公告)日:2006-04-13

    申请号:US10960609

    申请日:2004-10-07

    IPC分类号: G06F9/46

    CPC分类号: G06F9/322 G06F8/41 G06F9/3851

    摘要: A System and method for hiding memory latency in a multi-thread environment is presented. Branch Indirect and Set Link (BISL) and/or Branch Indirect and Set Link if External Data (BISLED) instructions are placed in thread code during compilation at instances that correspond to a prolonged instruction. A prolonged instruction is an instruction that instigates latency in a computer system, such as a DMA instruction. When a first thread encounters a BISL or a BISLED instruction, the first thread passes control to a second thread while the first thread's prolonged instruction executes. In turn, the computer system masks the latency of the first thread's prolonged instruction. The system can be optimized based on the memory latency by creating more threads and further dividing a register pool amongst the threads to further hide memory latency in operations that are highly memory bound.

    摘要翻译: 提出了一种在多线程环境中隐藏内存延迟的系统和方法。 分支间接和设置链接(BISL)和/或分支间接和设置链接,如果外部数据(BISLED)指令在对应于延长的指令的实例的编译期间被放置在线程代码中。 延长的指令是指示计算机系统中的延迟,例如DMA指令。 当第一个线程遇到BISL或BISLED指令时,第一个线程在第一个线程的延长指令执行时将控制传递给第二个线程。 反过来,计算机系统掩盖了第一个线程延长的指令的延迟。 可以通过创建更多线程并在线程之间进一步划分寄存器池来进一步隐藏高度内存限制的操作中的内存延迟,从而基于内存延迟来优化系统。

    System and method for compiling source code for multi-processor environments
    8.
    发明申请
    System and method for compiling source code for multi-processor environments 审中-公开
    用于编译多处理器环境的源代码的系统和方法

    公开(公告)号:US20050071828A1

    公开(公告)日:2005-03-31

    申请号:US10671056

    申请日:2003-09-25

    IPC分类号: G06F9/45

    CPC分类号: G06F9/44547 G06F8/447

    摘要: A system and method for compiling source code for multi-processor environments is presented. Source code is compiled which creates an object file whereby the object file includes multiple object code subtasks. Source code subtasks are compiled into object code subtasks using one of three approaches which are 1) a lowbrow approach, 2) a brute force approach, and 3) a program directive approach. Each object code subtask is formatted to run on a particular processor type with a particular architecture, such as a microprocessor-based architecture or a digital signal processor-based architecture. During runtime, each object code is loaded onto its corresponding processor type for execution.

    摘要翻译: 介绍了一种用于编译多处理器环境的源代码的系统和方法。 源代码被编译,其创建目标文件,由此目标文件包括多个目标代码子任务。 使用三种方法之一将源代码子任务编译为目标代码子任务,这三种方法之一是低级方法,2)强力方法,以及3)程序指令方法。 每个目标代码子任务被格式化为在具有特定架构的特定处理器类型上运行,例如基于微处理器的架构或基于数字信号处理器的架构。 在运行时,每个目标代码被加载到其相应的处理器类型上以供执行。

    Unidirectional message masking and validation system and method
    9.
    发明授权
    Unidirectional message masking and validation system and method 有权
    单向消息屏蔽和验证系统和方法

    公开(公告)号:US08024574B2

    公开(公告)日:2011-09-20

    申请号:US10763079

    申请日:2004-01-22

    IPC分类号: H04L9/32

    CPC分类号: H04L9/0662 H04L2209/04

    摘要: A system for secure communication is provided. A random value generator is configured to generate a random value. A message validation code generator is coupled to the random value generator and configured to generate a message validation code based on a predetermined key, a message, and the random value. A one-time pad generator is coupled to the random number generator and configured to generate a one-time pad based on the random value and the predetermined key. And a masked message generator is coupled to the one-time pad generator and configured to generate a masked message based on the one-time pad and the message. A protected message envelope generator is coupled to the random value generator, the message validation code generator, and the masked message generator, and is configured to generate a protected message envelope based on the random value, the message validation code, and the masked message.

    摘要翻译: 提供了用于安全通信的系统。 随机值生成器被配置为生成随机值。 消息验证码发生器耦合到随机值生成器并且被配置为基于预定密钥,消息和随机值生成消息验证码。 一次性垫发生器耦合到随机数发生器并且被配置为基于随机值和预定密钥生成一次性焊盘。 并且屏蔽的消息发生器耦合到一次性衬垫发生器并且被配置为基于一次性焊盘和消息来生成屏蔽消息。 受保护的消息包络生成器耦合到随机值生成器,消息验证码生成器和掩蔽消息生成器,并且被配置为基于随机值,消息验证码和掩蔽消息来生成受保护的消息包络。

    Methods for supplying cryptographic algorithm constants to a storage-constrained target
    10.
    发明申请
    Methods for supplying cryptographic algorithm constants to a storage-constrained target 有权
    将密码算法常数提供给存储受限目标的方法

    公开(公告)号:US20050132190A1

    公开(公告)日:2005-06-16

    申请号:US10733935

    申请日:2003-12-10

    IPC分类号: H04L9/32 H04L9/00

    CPC分类号: H04L9/3242

    摘要: The present invention provides for authenticating a message. A security function is performed upon the message. The message is sent to a target. The output of the security function is sent to the target. At least one publicly known constant is sent to the target. The received message is authenticated as a function of at least a shared key, the received publicly known constants, the security function, the received message, and the output of the security function. If the output of the security function received by the target is the same as the output generated as a function of at least the received message, the received publicly known constants, the security function, and the shared key, neither the message nor the constants have been altered.

    摘要翻译: 本发明提供用于认证消息。 对消息执行安全功能。 该消息被发送到目标。 安全功能的输出被发送到目标。 至少有一个公认的常数被发送到目标。 接收到的消息被认证为至少共享密钥,接收的公知常数,安全功能,接收到的消息和安全功能的输出的功能。 如果目标接收到的安全功能的输出与至少作为接收到的消息的函数产生的输出相同,则所接收的公知常数,安全功能和共享密钥,消息和常数都不具有 被改变了