公开(公告)号：US20110001873A1

公开(公告)日：2011-01-06

申请号：US12727796

申请日：2010-03-19

申请人： Daniel Doswald ,  Michael Joseph Erwin ,  Samir Narayan Hulyalkar

发明人： Daniel Doswald ,  Michael Joseph Erwin ,  Samir Narayan Hulyalkar

IPC分类号： H04N7/01

CPC分类号： H04N7/013

摘要： A frame rate converter device and method for interpolation during frame rate conversion are disclosed. The method includes, receiving input frames containing film content and video content. The film content exhibits a 3:2 pull-down cadence while video content that does not exhibit such cadence. Consecutive frames Cn and Cn+1 are interpolated to form Fn using the frame rate converter. The frame rate converter further selects as an output frame, either current or previous ones of interpolated frames or input frames. The selection is made so as to reduce both film judder and video judder. The invention is suitable for use on video input frames at 60 frames per second (fps) derived from a 24 fps cinema using 3:2 pull-down, and also blended with 60 Hz overlay video such as subtitle text. The invention can be used to obtain a good overall reduction in both overlay video judder and film judder.

摘要翻译： 公开了一种帧速率转换器装置和帧速转换时的插值方法。 该方法包括：接收包含电影内容和视频内容的输入帧。 电影内容呈现出3：2的下拉式节奏，而视频内容则不表现出这样的节奏。 连续帧Cn和Cn + 1被内插以使用帧速率转换器形成Fn。 帧速率转换器进一步选择内插帧或输入帧中的当前帧或前一帧的输出帧。 进行选择以减少胶片抖动和视频抖动。 本发明适用于从使用3：2下拉的24 fps影院得到的每秒60帧（fps）的视频输入帧，并且与60Hz重叠视频（例如字幕文本）混合使用。 本发明可以用于在重叠视频抖动和胶片抖动中获得良好的整体减小。

公开(公告)号：US6141384A

公开(公告)日：2000-10-31

申请号：US800637

申请日：1997-02-14

申请人： Karl Raymond Wittig ,  Samir Narayan Hulyalkar

发明人： Karl Raymond Wittig ,  Samir Narayan Hulyalkar

IPC分类号： H04N7/26 ,  H03M13/23 ,  H03M13/25 ,  H03M13/27 ,  H03M13/41 ,  H04N21/2383 ,  H04N21/438 ,  H04N7/12

CPC分类号： H03M13/256 ,  H03M13/2703 ,  H03M13/3961 ,  H03M13/4107 ,  H03M13/4169 ,  H03M13/6502 ,  H03M13/6508 ,  H04N21/2383 ,  H04N21/4382

摘要： In the standard format now adapted by FCC for a digital HDTV signal, the video data symbols are interleaved and trellis encoded in accordance with a 4-state trellis code and the interleaving is of sequences of every 12 successive symbols. At the receiver the trellis decoder is therefore projected to consist of 12 respective decoder stages for the 12 interleaved sequences, each decoder stage having a branch metric calculator unit (BMC), an add-compare-select (ACS) unit and a path memory unit (PMU). The present invention separates the path memory requirements for the 12 interleaved sequences from the requisite BMC and ACS functions, so that the latter two units can provide those functions for all of the 12 interleaved sequences. A single extended PMU provides for storage of pointers to possible predecessor states of the trellis code corresponding to a present state thereof, going back to a predetermined number (such as 16) of sequentially preceding received symbol values. The PMU also provides, in each of the storage stages, sequential storage elements corresponding to the sequential interleaved symbol values. This makes it possible for the PMU to be realized as a single integrated RAM by appropriate grouping of the trellis code states. Also, the ACS function is performed by two separate ACS units for two mutually independent groups of trellis code states.

摘要翻译： 在现在由FCC适用于数字HDTV信号的标准格式中，视频数据符号根据4状态网格码进行交织和格网编码，并且交织是每12个连续符号的序列。 因此，在接收机处，网格解码器被投射为12个交错序列的12个相应的解码器级，每个解码器级具有分支度量计算器单元（BMC），加法比较选择（ACS）单元和路径存储器单元 （PMU）。 本发明将12个交错序列的路径存储器要求与必要的BMC和ACS功能分离，使得后两个单元可以为12个交错序列中的全部提供那些功能。 单个扩展PMU提供用于存储指向与其当前状态相对应的格状码的可能的先前状态的指针，返回到先前接收的符号值的预定数量（例如16）。 PMU还在每个存储级中提供与顺序交织的符号值相对应的顺序存储元件。 这使得PMU可以通过适当地分组格状态来实现为单个集成RAM。 此外，ACS功能由两个独立的ACS单元执行，用于两个相互独立的网格码状态组。