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16 条记录 (耗时 0.03 秒)

    Phase detector
    1.
    发明授权
    Phase detector 失效
    相位检测器

    公开(公告)号：US06762626B1

    公开(公告)日：2004-07-13

    申请号：US10422686

    申请日：2003-04-24

    申请人： Daniel Mark Dreps ,  Frank David Ferraiolo ,  Kevin Charles Gower ,  Gary Alan Peterson ,  Robert James Reese

    发明人： Daniel Mark Dreps ,  Frank David Ferraiolo ,  Kevin Charles Gower ,  Gary Alan Peterson ,  Robert James Reese

    IPC分类号： H03D900

    CPC分类号： H03D13/004

    摘要： A phase detector for use in conjunction with a delay locked loop is provided. Programmable delay elements insert an adjustable delay in a received data stream. The programmable delays stress the setup and hold times of the incoming data. Phase detector sampling logic detects the phase difference between a nominal center of the data window, and the limits on the setup (early) edge of the data value window, and the hold time limit (late time) edge of the data valid window (“guardbands”). A data signal arriving earlier than an early guardband or later than a late guardband may not be correctly sampled, and a guardband failure may be said to have occurred. A state machine detects such guardband errors and provides corrective feedback signals.

    摘要翻译： 提供了一种与延迟锁定环结合使用的相位检测器。 可编程延迟元件在接收的数据流中插入可调延迟。 可编程延迟会强制输入数据的建立和保持时间。 相位检测器采样逻辑检测数据窗口的标称中心与数据值窗口的设置（早期）边沿的限制以及数据有效窗口的保持时间限制（后期）边沿之间的相位差（“ 护卫队“）。 在早期保护带之前到达晚于后期保护带的数据信号可能未被正确采样，并且可能说已经发生了保护带故障。 状态机检测这种保护带错误并提供校正反馈信号。

    Self-healing chip-to-chip interface
    2.
    发明授权
    Self-healing chip-to-chip interface 失效
    自愈芯片到芯片的接口

    公开(公告)号：US07362697B2

    公开(公告)日：2008-04-22

    申请号：US10339757

    申请日：2003-01-09

    申请人： Wiren Dale Becker ,  Daniel Mark Dreps ,  Frank David Ferraiolo ,  Anand Haridass ,  Robert James Reese

    发明人： Wiren Dale Becker ,  Daniel Mark Dreps ,  Frank David Ferraiolo ,  Anand Haridass ,  Robert James Reese

    IPC分类号： G01R31/08

    CPC分类号： H01L22/22 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method, apparatus, and computer instructions for managing a set of signal paths for a chip. A defective signal path within the set of signal paths for the chip is detected. Signals are re-routed through the set of signal paths such that the defective signal path is removed from the set of signal paths and sending signals using remaining data signal paths in the set of signal paths and using an extra signal path in response to detecting the defective signal path.

    摘要翻译： 一种用于管理用于芯片的一组信号路径的方法，装置和计算机指令。 检测用于芯片的信号路径集合内的有缺陷的信号路径。 信号通过一组信号路径重新路由，使得有缺陷的信号路径从信号路径集合中移除，并使用信号路径组中的剩余数据信号路径发送信号，并且响应于检测到的信号路径 有缺陷的信号路径。

    Self-Healing Chip-to-Chip Interface
    4.
    发明申请
    Self-Healing Chip-to-Chip Interface 失效
    自我修复芯片到芯片接口

    公开(公告)号：US20110010482A1

    公开(公告)日：2011-01-13

    申请号：US12886404

    申请日：2010-09-20

    申请人： Wiren Dale Becker ,  Daniel Mark Dreps ,  Frank David Ferraiolo ,  Anand Haridass ,  Robert James Reese

    发明人： Wiren Dale Becker ,  Daniel Mark Dreps ,  Frank David Ferraiolo ,  Anand Haridass ,  Robert James Reese

    IPC分类号： G06F13/00

    CPC分类号： H01L22/22 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method, apparatus, and computer instructions for managing a set of signal paths for a chip. A defective signal path within the set of signal paths for the chip is detected. Signals are re-routed through the set of signal paths such that the defective signal path is removed from the set of signal paths and sending signals using remaining data signal paths in the set of signal paths and using an extra signal path in response to detecting the defective signal path.

    摘要翻译： 一种用于管理用于芯片的一组信号路径的方法，装置和计算机指令。 检测用于芯片的信号路径集合内的有缺陷的信号路径。 信号通过一组信号路径重新路由，使得有缺陷的信号路径从信号路径集合中移除，并使用信号路径组中的剩余数据信号路径发送信号，并且响应于检测到的信号路径 有缺陷的信号路径。

    Self-healing chip-to-chip interface
    5.
    发明授权
    Self-healing chip-to-chip interface 有权
    自愈芯片到芯片的接口

    公开(公告)号：US07813266B2

    公开(公告)日：2010-10-12

    申请号：US11948620

    申请日：2007-11-30

    申请人： Wiren Dale Becker ,  Daniel Mark Dreps ,  Frank David Ferraiolo ,  Anand Haridass ,  Robert James Reese

    发明人： Wiren Dale Becker ,  Daniel Mark Dreps ,  Frank David Ferraiolo ,  Anand Haridass ,  Robert James Reese

    IPC分类号： G01R31/08

    CPC分类号： H01L22/22 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method, apparatus, and computer instructions for managing a set of signal paths for a chip. A defective signal path within the set of signal paths for the chip is detected. Signals are re-routed through the set of signal paths such that the defective signal path is removed from the set of signal paths and sending signals using remaining data signal paths in the set of signal paths and using an extra signal path in response to detecting the defective signal path.

    摘要翻译： 一种用于管理用于芯片的一组信号路径的方法，装置和计算机指令。 检测用于芯片的信号路径集合内的有缺陷的信号路径。 信号通过一组信号路径重新路由，使得有缺陷的信号路径从信号路径集合中移除，并使用信号路径组中的剩余数据信号路径发送信号，并且响应于检测到的信号路径 有缺陷的信号路径。

    Self-Healing Chip-to-Chip Interface
    6.
    发明申请
    Self-Healing Chip-to-Chip Interface 失效
    自我修复芯片到芯片接口

    公开(公告)号：US20100085872A1

    公开(公告)日：2010-04-08

    申请号：US12635121

    申请日：2009-12-10

    申请人： Wiren Dale Becker ,  Daniel Mark Dreps ,  Frank David Ferraiolo ,  Anand Haridass ,  Robert James Reese

    发明人： Wiren Dale Becker ,  Daniel Mark Dreps ,  Frank David Ferraiolo ,  Anand Haridass ,  Robert James Reese

    IPC分类号： H04L12/26

    CPC分类号： H01L22/22 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method, apparatus, and computer instructions for managing a set of signal paths for a chip. A defective signal path within the set of signal paths for the chip is detected. Signals are re-routed through the set of signal paths such that the defective signal path is removed from the set of signal paths and sending signals using remaining data signal paths in the set of signal paths and using an extra signal path in response to detecting the defective signal path.

    摘要翻译： 一种用于管理用于芯片的一组信号路径的方法，装置和计算机指令。 检测用于芯片的信号路径集合内的有缺陷的信号路径。 信号通过一组信号路径重新路由，使得有缺陷的信号路径从信号路径集合中移除，并使用信号路径组中的剩余数据信号路径发送信号，并且响应于检测到的信号路径 有缺陷的信号路径。

    Method and apparatus for interface failure survivability using error correction
    7.
    发明授权
    Method and apparatus for interface failure survivability using error correction 有权
    使用纠错的接口故障生存性的方法和装置

    公开(公告)号：US07080288B2

    公开(公告)日：2006-07-18

    申请号：US10425423

    申请日：2003-04-28

    申请人： Frank David Ferraiolo ,  Michael Stephen Floyd ,  Robert James Reese ,  Kevin Franklin Reick

    发明人： Frank David Ferraiolo ,  Michael Stephen Floyd ,  Robert James Reese ,  Kevin Franklin Reick

    IPC分类号： G06F11/22

    CPC分类号： H04L43/50 ,  G06F11/221 ,  H04L1/00 ,  H04L1/242

    摘要： A method an apparatus for interface failure survivability using error correction provides operation of an interface when a number of bits of the interface less than or equal to available error correction depth are present. Initialization tests are used to determine whether the interface errors due to failed interconnects or circuits can be corrected, or whether the interface must be disabled. Subsequent alignment at initialization or during operation idle periods may be disabled for any failed bit paths. The failed bit path indications are determined and maintained in hardware, and used to bypass subsequent calibrations that could otherwise corrupt the interface. A fault indication specifying total failure may be generated and used to shut down the interface and/or connected subsystem in response to an uncorrectable condition and request immediate repair. A second fault indication specifying correctable failure may be generated and used to indicate a need for eventual repair.

    摘要翻译： 一种使用错误校正的接口故障生存性的装置的方法提供当接口的位数小于或等于可用纠错深度时的接口的操作。 初始化测试用于确定由于互连或电路故障导致的接口错误是否可以更正，还是禁用接口。 对于任何故障的位路径，在初始化或操作空闲期间的后续对齐可被禁用。 失败的位路径指示被确定并维护在硬件中，并用于绕过可能会破坏接口的后续校准。 可以产生指示全部故障的故障指示并用于响应于不可校正的状况而关闭接口和/或连接的子系统并请求立即修复。 可以产生指示可修正故障的第二故障指示并用于指示最终修复的需要。

    Method and system for enhanced efficiency of data transfers from memory to multiple processors in a data processing system
    9.
    发明授权
    Method and system for enhanced efficiency of data transfers from memory to multiple processors in a data processing system 失效
    用于提高数据处理系统中从存储器到多个处理器的数据传输效率的方法和系统

    公开(公告)号：US5793986A

    公开(公告)日：1998-08-11

    申请号：US551396

    申请日：1995-11-01

    申请人： Michael Scott Allen ,  Charles Roberts Moore ,  Robert James Reese

    发明人： Michael Scott Allen ,  Charles Roberts Moore ,  Robert James Reese

    IPC分类号： G06F15/16 ,  G06F12/08 ,  G06F15/177 ,  G06F13/00

    CPC分类号： G06F12/0831

    摘要： A method and system for the enhanced efficiency of data transfers from memory to multiple processors in a data processing system. Each of the multiple processors has an associated buffer for storing data transferred via a common bus which couples the processors and memory together. Each of the multiple processors continually monitors the common bus and is capable of asserting a selected control signal in response to an attempted activity of another one of the multiple processors which would violate data coherency within the data processing system during a particular period of time following the attempted activity. Data is transferred from memory to a buffer associated with one of the multiple processors and stored in the buffer in response to a request from the processor associated with the buffer prior to expiration of the particular period of time and prior to a determination of whether or not this transfer will result in a possible data coherency problem. The common bus is continually monitored during the particular period of time. Transfer of the data from the buffer to the processor is prohibited in response to a presence on the common bus of the selected control signal prior to expiration of the particular of time. Transfer of the data from the buffer to the processor is permitted in response to an absence on the common bus of the selected control signal.

    摘要翻译： 一种用于在数据处理系统中从存储器到多个处理器的数据传输的增强效率的方法和系统。 多个处理器中的每一个具有用于存储经由公共总线传送的数据的相关联的缓冲器，该公共总线将处理器和存储器耦合在一起。 多个处理器中的每一个持续地监视公共总线，并且能够响应于多个处理器中的另一个处理器的尝试的活动来断言所选择的控制信号，这将在数据处理系统中的特定时间段内违反数据一致性 尝试活动。 数据从存储器传送到与多个处理器中的一个处理器相关联的缓冲器，并且响应于在特定时间段到期之前和在确定之前的处理器与缓冲器相关联的处理器的请求而被存储在缓冲器中 这种传输将导致可能的数据一致性问题。 公共巴士在特定时期内不断监控。 响应于在特定时间到期之前在公共总线上存在所选择的控制信号，禁止将数据从缓冲器传送到处理器。 响应于所选控制信号的公共总线上的不存在，允许将数据从缓冲器传送到处理器。

    Method and system for achieving atomic memory references in a multilevel cache data processing system
    10.
    发明授权
    Method and system for achieving atomic memory references in a multilevel cache data processing system 失效
    用于在多级缓存数据处理系统中实现原子存储器引用的方法和系统

    公开(公告)号：US5706464A

    公开(公告)日：1998-01-06

    申请号：US608978

    申请日：1996-02-29

    申请人： Charles Roberts Moore ,  John Stephen Muhich ,  Robert James Reese

    发明人： Charles Roberts Moore ,  John Stephen Muhich ,  Robert James Reese

    IPC分类号： G06F15/16 ,  G06F12/08 ,  G06F15/177 ,  G06F12/12

    CPC分类号： G06F12/0811

    摘要： Atomic memory references require a data processing system to present the appearance of a coherent memory system, which may be achieved in most multiprocessor systems by means of normal memory coherency systems. Writes or attempted writes to memory must be monitored by a processor in order to correctly resolve hits against the reservation state. In a two level cache system the second level cache filters bus operations and forwards to the processor any bus traffic that may involve data stored within the first level cache. This may be accomplished by enforcing an "inclusion" property wherein all data entries within the first level cache are required to be maintained within higher level caches. A problem arises when a block within a first level cache which has had a reservation pending is cast out and the second level cache no longer forwards bus traffic to the associated processor, despite the continued pendency of the reservation. This problem is avoided by setting a reservation flag each time a valid reservation is pending. Thereafter, any replacement of a data entry in a higher level cache results in the automatic deletion of the corresponding data entry within any included level of cache. The reservation flag is then reset in response to the occurrence of either a bus operation which affects the reservation address or the deletion of the cache data entry corresponding to the reservation address, permitting atomic memory references to be achieved without the necessity of distributing the reservation address.

    摘要翻译： 原子存储器引用要求数据处理系统呈现一个相干存储器系统的外观，这可以通过一般存储器一致性系统在大多数多处理器系统中实现。 对存储器的写入或尝试写入必须由处理器监视，以便正确地解决针对预留状态的命中。 在二级高速缓存系统中，第二级缓存过滤总线操作并向处理器转发可能涉及存储在第一级高速缓存内的数据的任何总线流量。 这可以通过实施“包含”属性来实现，其中第一级高速缓存中的所有数据条目需要被保持在更高级别的高速缓存中。 当具有预留待处理的第一级高速缓冲存储器中的块被抛弃并且尽管保留的持续性仍然存在时，第二级高速缓存不再将总线流量转发到相关联的处理器。 每当一个有效的保留待定时，设置一个保留标志来避免这个问题。 此后，任何替换较高级别高速缓存中的数据条目导致在任何包含的高速缓存级别内自动删除相应的数据条目。 响应于影响预约地址的总线操作的发生或与预约地址相对应的高速缓存数据条目的删除，保留标志被复位，从而允许实现原子存储器引用而不需要分发预留地址 。