Adaptive comparison control in a data store
    1.
    发明授权
    Adaptive comparison control in a data store 有权
    数据存储中的自适应比较控制

    公开(公告)号:US07991960B2

    公开(公告)日:2011-08-02

    申请号:US12230333

    申请日:2008-08-27

    IPC分类号: G06F12/00

    摘要: Data store access circuitry is disclosed that comprises: a data store for storing values; comparator circuitry coupled to said data store and responsive to receipt of a data access request comprising an address to compare at least a portion of said address with at least a portion of one or more of said values stored in said data store so as to identify a stored value matching said address; a base value register coupled to said comparator circuitry and storing a base value corresponding to at least a portion of at least one of said stored values; and comparator control circuitry coupled to said comparator circuitry to control: (i) which portion of said address is processed as a non-shared portion and compared by said comparator circuitry with non-shared portions of said one or more stored values stored in said data store; and (ii) which portion of said address is processed as a shared portion and compared by said comparator circuitry with a shared portion of said base value stored in said base value register; wherein said shared portion of said base value has a value matching corresponding portions of all of said stored values stored within said data store.

    摘要翻译: 公开了一种数据存储器访问电路,其包括:用于存储值的数据存储器; 比较器电路,耦合到所述数据存储器并且响应于接收包括地址的数据访问请求,以将所述地址的至少一部分与存储在所述数据存储器中的一个或多个所述值的至少一部分进行比较,以便识别 存储值匹配所述地址; 基值寄存器,耦合到所述比较器电路并存储对应于所述存储值中的至少一个的至少一部分的基值; 和比较器控制电路,其耦合到所述比较器电路以控制:(i)所述地址的哪个部分被处理为非共享部分,并由所述比较器电路与所存储在所述数据中的所述一个或多个存储值的非共享部分进行比较 商店; 和(ii)所述地址的哪个部分被处理为共享部分,并由所述比较器电路与存储在所述基值寄存器中的所述基值的共享部分进行比较; 其中所述基本值的所述共享部分具有匹配存储在所述数据存储器内的所有所述存储值的相应部分的值。

    Adaptive comparison control in a memory
    2.
    发明授权
    Adaptive comparison control in a memory 有权
    内存中的自适应比较控制

    公开(公告)号:US07640397B2

    公开(公告)日:2009-12-29

    申请号:US11545758

    申请日:2006-10-11

    IPC分类号: G06F13/00

    摘要: A memory has multiple memory rows 32 storing respective stored values. The stored values are divided into portions which may be shared by all stored values within the memory rows concerned. When such portions are so shared, then the comparison between an input value and the plurality of stored values can be performed using a base value stored within a base value register 30 rather than by reading the relevant portions of the memory rows. Thus, those relevant portions of the memory rows can be disabled and power saved.

    摘要翻译: 存储器具有存储相应存储值的多个存储器行32。 存储的值被划分成可以被相关存储器行内的所有存储值共享的部分。 当这样的部分如此共享时,可以使用存储在基值寄存器30内的基值进行输入值与多个存储值之间的比较,而不是通过读取存储器行的相关部分。 因此,可以禁用存储器行的相关部分并省电。

    Adaptive comparison control in a data store
    3.
    发明申请
    Adaptive comparison control in a data store 有权
    数据存储中的自适应比较控制

    公开(公告)号:US20090100054A1

    公开(公告)日:2009-04-16

    申请号:US12230333

    申请日:2008-08-27

    IPC分类号: G06F17/30 G06F12/10

    摘要: Data store access circuitry is disclosed that comprises: a data store for storing values; comparator circuitry coupled to said data store and responsive to receipt of a data access request comprising an address to compare at least a portion of said address with at least a portion of one or more of said values stored in said data store so as to identify a stored value matching said address; a base value register coupled to said comparator circuitry and storing a base value corresponding to at least a portion of at least one of said stored values; and comparator control circuitry coupled to said comparator circuitry to control: (i) which portion of said address is processed as a non-shared portion and compared by said comparator circuitry with non-shared portions of said one or more stored values stored in said data store; and (ii) which portion of said address is processed as a shared portion and compared by said comparator circuitry with a shared portion of said base value stored in said base value register; wherein said shared portion of said base value has a value matching corresponding portions of all of said stored values stored within said data store.

    摘要翻译: 公开了一种数据存储器访问电路,其包括:用于存储值的数据存储器; 比较器电路,耦合到所述数据存储器并且响应于接收包括地址的数据访问请求,以将所述地址的至少一部分与存储在所述数据存储器中的一个或多个所述值的至少一部分进行比较,以便识别 存储值匹配所述地址; 基值寄存器,耦合到所述比较器电路并存储对应于所述存储值中的至少一个的至少一部分的基值; 和比较器控制电路,其耦合到所述比较器电路以控制:(i)所述地址的哪个部分被处理为非共享部分,并由所述比较器电路与所存储在所述数据中的所述一个或多个存储值的非共享部分进行比较 商店; 和(ii)所述地址的哪个部分被处理为共享部分,并由所述比较器电路与存储在所述基值寄存器中的所述基值的共享部分进行比较; 其中所述基本值的所述共享部分具有匹配存储在所述数据存储器内的所有所述存储值的相应部分的值。

    Cache memory system for a data processing apparatus
    4.
    发明申请
    Cache memory system for a data processing apparatus 审中-公开
    用于数据处理装置的高速缓冲存储器系统

    公开(公告)号:US20090055589A1

    公开(公告)日:2009-02-26

    申请号:US11892667

    申请日:2007-08-24

    IPC分类号: G06F12/00

    摘要: A data processing apparatus is provided having a cache memory 262, 264, a cache controller 240 and a location-specifying memory 252. The location-specifying memory is configured to store mapping data providing a mapping between a given memory address and a storage location in the cache. The stored mapping data is used instead of performing a cache look up to access the information corresponding to the given memory address in the cache memory. Furthermore, a data processing apparatus is provided having a pipelined processing circuit 220, a cache memory 262, 264, loop detection circuitry, branch prediction circuitry 232 and control circuitry 240. The branch prediction circuitry is configured to generate branch prediction information, which is used by the control circuitry to control which program instructions of detected program loops are stored by the buffer memory.

    摘要翻译: 提供了具有高速缓冲存储器262,264,高速缓存控制器240和位置指定存储器252的数据处理装置。位置指定存储器被配置为存储提供给定存储器地址和存储位置之间的映射的映射数据 缓存。 使用所存储的映射数据而不是执行高速缓存查找以访问与高速缓冲存储器中的给定存储器地址相对应的信息。 此外,提供了具有流水线处理电路220,高速缓冲存储器262,264,环路检测电路,分支预测电路232和控制电路240的数据处理装置。分支预测电路被配置为生成分支预测信息,其被使用 由控制电路控制由缓冲存储器存储检测到的程序循环的哪些程序指令。

    Adaptive comparison control in a memory
    5.
    发明申请
    Adaptive comparison control in a memory 有权
    内存中的自适应比较控制

    公开(公告)号:US20080091882A1

    公开(公告)日:2008-04-17

    申请号:US11545758

    申请日:2006-10-11

    IPC分类号: G06F12/00

    摘要: A memory has multiple memory rows 32 storing respective stored values. The stored values are divided into portions which may be shared by all stored values within the memory rows concerned. When such portions are so shared, then the comparison between an input value and the plurality of stored values can be performed using a base value stored within a base value register 30 rather than by reading the relevant portions of the memory rows. Thus, those relevant portions of the memory rows can be disabled and power saved.

    摘要翻译: 存储器具有存储相应存储值的多个存储器行32。 存储的值被划分成可以被相关存储器行内的所有存储值共享的部分。 当这样的部分如此共享时,可以使用存储在基值寄存器30内的基值进行输入值与多个存储值之间的比较,而不是通过读取存储器行的相关部分。 因此,可以禁用存储器行的相关部分并省电。