公开(公告)号：US20050025277A1

公开(公告)日：2005-02-03

申请号：US10604550

申请日：2003-07-30

申请人： Darren Anand ,  John Goss ,  Peter Jakobsen ,  Michael Ouellette ,  Thomas Sopchak ,  Donald Wheater

发明人： Darren Anand ,  John Goss ,  Peter Jakobsen ,  Michael Ouellette ,  Thomas Sopchak ,  Donald Wheater

IPC分类号： G11C19/00 ,  G11C29/00

CPC分类号： G11C19/00 ,  G11C29/003

摘要： The invention provides a circuit that can observe data within shift registers without altering the data. The circuit includes selectors connected to the inputs and outputs of the shift registers. The selectors selectively connect the input with the output of a selected shift register to form a wiring loop for the selected shift register. A control device connected to the wiring loop uses the wiring loop to cause the data to be continually transferred from the output of the selected shift register to the input of the selected shift register and back through the selected shift register in a circular manner. The control device includes a counter used for determining the length of a selected shift register and a set of registers to store, for future use when rotating data in the shift registers, the length of each shift register. The control device also includes a data output accessible from outside the circuit. An observation wire is connected to the wiring loop, and the data passes from the wiring loop to the control device through the observation wire. The control device outputs data appearing on the wiring loop as the data is circulated through the selected shift register to permit data within the selected shift register to be observed outside the circuit without altering the data within the selected shift register.

摘要翻译： 本发明提供一种可以观察移位寄存器内的数据而不改变数据的电路。 该电路包括连接到移位寄存器的输入和输出的选择器。 选择器选择性地将输入与所选移位寄存器的输出连接，以形成所选移位寄存器的布线回路。 连接到布线回路的控制装置使用布线回路使得数据从所选择的移位寄存器的输出连续地传送到所选择的移位寄存器的输入端并循环地返回所选择的移位寄存器。 控制装置包括用于确定所选择的移位寄存器的长度的计数器和一组寄存器，用于存储当在移位寄存器中旋转数据时将来使用的每个移位寄存器的长度。 控制装置还包括从电路外部可访问的数据输出。 观察线连接到布线回路，数据通过观察线从布线回路传递到控制装置。 当数据通过选定的移位寄存器循环时，控制装置输出出现在布线环路上的数据，以允许在电路外观察所选移位寄存器内的数据，而不改变所选移位寄存器内的数据。

公开(公告)号：US20070033458A1

公开(公告)日：2007-02-08

申请号：US11533907

申请日：2006-09-21

申请人： Darren Anand ,  John Goss ,  Peter Jacobsen ,  Michael Ouellette ,  Thomas Sopchak ,  Donald Wheater

发明人： Darren Anand ,  John Goss ,  Peter Jacobsen ,  Michael Ouellette ,  Thomas Sopchak ,  Donald Wheater

IPC分类号： G01R31/28

CPC分类号： G11C19/00 ,  G11C29/003

摘要： The invention provides a circuit that can observe data within shift registers without altering the data. The circuit includes selectors connected to the inputs and outputs of the shift registers. The selectors selectively connect the input with the output of a selected shift register to form a wiring loop for the selected shift register. A control device connected to the wiring loop uses the wiring loop to cause the data to be continually transferred from the output of the selected shift register to the input of the selected shift register and back through the selected shift register in a circular manner. The control device includes a counter used for determining the length of a selected shift register and a set of registers to store, for future use when rotating data in the shift registers, the length of each shift register. The control device also includes a data output accessible from outside the circuit. An observation wire is connected to the wiring loop, and the data passes from the wiring loop to the control device through the observation wire. The control device outputs data appearing on the wiring loop as the data is circulated through the selected shift register to permit data within the selected shift register to be observed outside the circuit without altering the data within the selected shift register.

摘要翻译： 本发明提供一种可以观察移位寄存器内的数据而不改变数据的电路。 该电路包括连接到移位寄存器的输入和输出的选择器。 选择器选择性地将输入与所选移位寄存器的输出连接，以形成所选移位寄存器的布线回路。 连接到布线回路的控制装置使用布线回路使得数据从所选择的移位寄存器的输出连续地传送到所选择的移位寄存器的输入端并循环地返回所选择的移位寄存器。 控制装置包括用于确定所选择的移位寄存器的长度的计数器和一组寄存器，用于存储当在移位寄存器中旋转数据时将来使用的每个移位寄存器的长度。 控制装置还包括从电路外部可访问的数据输出。 观察线连接到布线回路，数据通过观察线从布线回路传递给控制装置。 当数据通过选定的移位寄存器循环时，控制装置输出出现在布线环路上的数据，以允许在电路外观察所选移位寄存器内的数据，而不改变所选移位寄存器内的数据。

公开(公告)号：US20050013187A1

公开(公告)日：2005-01-20

申请号：US10604414

申请日：2003-07-18

申请人： Darren Anand ,  John Barth ,  Steven Oakland ,  Michael Ouellette

发明人： Darren Anand ,  John Barth ,  Steven Oakland ,  Michael Ouellette

IPC分类号： G11C17/00 ,  G11C17/16 ,  G11C17/18

CPC分类号： G11C17/16 ,  G11C17/18

摘要： A method and electrical fuse circuit design for reducing the testing time for a semiconductor device manufactured with redundant eFuse circuitry. A two-to-one multiplexer (MUX) is provided at each eFuse circuit in addition to the fuse latch and pattern latch and other logic components the eFuse circuit. Information on which fuse is to be blown is stored in the fuse's pattern latch. The output generated by the pattern latch is ANDed with a program input to provide a select signal for the MUX. Based on the select signal, the MUX allows the shifted “1” to either go to the next latch in the shift chain or bypass the next latch or latches in the shift chain depending on whether the next fuse is to be blown. Accordingly, rather than serially shifting through each fuse latch within the device, the invention enables only those fuse latches associated with fuses that are to be blown to hold up the propagation of the shifted “1” to the next eFuse circuits.

摘要翻译： 一种用于减少使用冗余eFuse电路制造的半导体器件的测试时间的方法和电熔丝电路设计。 除了保险丝锁存器和图案锁存器以及eFuse电路的其他逻辑元件之外，在每个eFuse电路上还提供两对一多路复用器（MUX）。 保险丝图案锁存器中存储有要熔断保险丝的信息。 由模式锁存器产生的输出与程序输入进行“与”运算以提供MUX的选择信号。 基于选择信号，MUX允许移位的“1”转到下一个锁存器，或者旁路下一个锁存器或锁存在换档链中，这取决于下一个保险丝是否被熔断。 因此，本发明不仅可以串联地转换器件内的每个熔丝锁存器，而且仅使与熔断器相关联的熔丝锁存器能够保持传输“1”到下一个eFuse电路的传输。

公开(公告)号：US20060239088A1

公开(公告)日：2006-10-26

申请号：US10908033

申请日：2005-04-26

申请人： Darren Anand ,  Michael Ouellette ,  Michael Ziegerhofer

发明人： Darren Anand ,  Michael Ouellette ,  Michael Ziegerhofer

IPC分类号： G11C29/00 ,  G11C7/00

CPC分类号： G11C17/165 ,  G11C29/027 ,  G11C29/4401 ,  G11C29/72

摘要： Integrated circuit memory is tested to discover defective memory elements. To replace the defective memory elements, spare memory elements are selected and a string is generated to indicate which ones of the spares replace which ones of the defective memory elements. The number of bits of the string depend upon how many of the memory elements are defective. Although a certain number of the memory elements are defective, which determines the number of the string bits, nevertheless, a number of fuses to program on the integrated circuit is determined responsive to how many fuses are available for programming relative to the number of the binary string bits. That is, if more fuses are available than a certain threshold number relative to the number of string bits (as is preferred), then more than the threshold number are programmed. If not, then only that certain threshold number of fuses are programmed.

摘要翻译： 测试集成电路存储器以发现有缺陷的存储器元件。 为了更换有缺陷的存储器元件，选择备用存储器元件，并且生成字符串以指示哪些备用件替换有缺陷存储器元件中的哪一个。 字符串的位数取决于多少存储器元件有缺陷。 尽管一定数量的存储器元件是有缺陷的，这确定了串比特的数目，然而，确定集成电路上编程的多个保险丝的响应是相对于二进制数的编号有多少个熔丝可用于编程 字符串位。 也就是说，如果比相对于字符串位数（优选的）更多的熔丝可用于某个阈值数，则多于阈值编号。 如果没有，那么只有该阈值数量的保险丝被编程。

公开(公告)号：US20090016129A1

公开(公告)日：2009-01-15

申请号：US11775531

申请日：2007-07-10

申请人： Darren Anand ,  Michael Ouellette ,  Michael Ziegerhofer

发明人： Darren Anand ,  Michael Ouellette ,  Michael Ziegerhofer

IPC分类号： G11C29/00

CPC分类号： G11C29/44 ,  G11C17/165 ,  G11C29/027 ,  G11C29/802

摘要： A design structure which enables e-fuse memory repair. The design structure uses a compressed bit string to generate another bit string based on a select value. The select value provides instructions to an encoding logic element, which generates a second bit string. For example, the select value may instruct the encoding logic to create a duplicate copy of each bit in the compressed bit string to generate a 2n-bit string. Once the fuses are programmed using the second bit string, the fuse values are read out as a third string, which is decoded by a decoding logic element according to the select value, thereby improving memory repair.

摘要翻译： 一种能够进行电子保险丝内存修复的设计结构。 设计结构使用压缩比特串根据选择值生成另一个比特串。 该选择值向编码逻辑元件提供指令，该编码逻辑元件产生第二位串。 例如，选择值可以指示编码逻辑在压缩比特串中创建每个比特的重复副本以生成2n比特串。 一旦使用第二位串编程熔丝，则将熔丝值作为第三串读出，其由解码逻辑元件根据选择值解码，从而改善存储器修复。

公开(公告)号：US20050050415A1

公开(公告)日：2005-03-03

申请号：US10604908

申请日：2003-08-26

申请人： Darren Anand ,  John Barth ,  Steven Oakland ,  Michael Ouellette

发明人： Darren Anand ,  John Barth ,  Steven Oakland ,  Michael Ouellette

IPC分类号： G01R31/3185 ,  G01R31/28

CPC分类号： G01R31/318536 ,  G01R31/318544

摘要： A method and circuit design for enabling both shift path and scan path functionality with a single port LSSD latch designed for scan path functionality only, without increasing the device's internal real estate and without substantial increase in overall device real estate. The circuit design eliminates the need for additional logic components to be built into the internal circuitry of the device and also eliminates the cost of providing dual port LSSD latches within the device. Implementation of the invention involves providing a unique configuration of low level logic components as input circuitry that is coupled to a pair of single port LSSD latches that operate as the input latches for the device. The low level logic components accomplishes the splitting of scan chain inputs and shift chain inputs to the input latches and thus enables the single ported LSSD latches to operate with similar functionality as dual ported LSSD latches.

摘要翻译： 一种方法和电路设计，用于仅使用设计用于扫描路径功能的单端口LSSD锁存器实现移位路径和扫描路径功能，而不会增加设备的内部房地产，而且整体设备的不动产不会大幅增加。 电路设计消除了对设备内部电路内置的其他逻辑元件的需求，并且消除了在器件内提供双端口LSSD锁存器的成本。 本发明的实现涉及提供作为输入电路的低级逻辑组件的独特配置，该输入电路耦合到作为设备的输入锁存器操作的一对单端口LSSD锁存器。 低电平逻辑组件完成扫描链输入和移位链输入到输入锁存器的分割，从而使单端口LSSD锁存器能够与双端口LSSD锁存器类似的功能运行。

公开(公告)号：US20200029542A1

公开(公告)日：2020-01-30

申请号：US15998281

申请日：2018-07-30

申请人： Michael Ouellette

发明人： Michael Ouellette

IPC分类号： A01K97/08 ,  A01K87/02 ,  A01K87/04

摘要： This invention provides an outrigger assembly for fishing that can be quickly deployed from a portable bag about 1 meter long into a fully rigged outrigger in a selected length of 4 meters, 5 meters or 6 meters. Variable length is obtained by adding sections of telescoping pole. Quick deployment is obtained by using detachable line guides that are radially (or side) threadable in conjunction with a separate preassembled outrigger line loop for each deployed length. Different length outrigger line loop assemblies are color coded for quick identification. Stowed length and volume of the collapsed telescoping pole is minimized by the use of outrigger line guides that are removable from the outrigger pole. Threading and unthreading of an outrigger line loop without opening the loop is enabled by the radially threadable line guides. The invention also provides an outrigger holder having two sockets, one for the outrigger and one for a fishing pole.

公开(公告)号：US20080037341A1

公开(公告)日：2008-02-14

申请号：US11875011

申请日：2007-10-19

申请人： Michael Ouellette ,  Jeremy Rowland

发明人： Michael Ouellette ,  Jeremy Rowland

IPC分类号： G11C29/00

CPC分类号： G11C29/4401 ,  G11C29/14 ,  G11C29/24 ,  G11C29/44

摘要： Methods and apparatuses for enabling a redundant memory element (20) during testing of a memory array (14). The memory array (14) includes general memory elements (18) and redundant memory elements (20). The general memory elements (18) are tested and any defective general memory elements (18) are replaced with redundant memory elements (20). The redundant memory elements (20) are tested only when they are enabled.

摘要翻译： 用于在存储器阵列（14）的测试期间启用冗余存储元件（20）的方法和装置。 存储器阵列（14）包括通用存储元件（18）和冗余存储元件（20）。 一般存储器元件（18）被测试，并且任何有缺陷的通用存储器元件（18）被替换为冗余存储元件（20）。 冗余存储器元件（20）仅在使能时被测试。

公开(公告)号：US20070258296A1

公开(公告)日：2007-11-08

申请号：US11418052

申请日：2006-05-04

申请人： Arthur Bright ,  Paul Crumley ,  Marc Dombrowa ,  Steven Douskey ,  Rudolf Haring ,  Steven Oakland ,  Michael Ouellette ,  Scott Strissel

发明人： Arthur Bright ,  Paul Crumley ,  Marc Dombrowa ,  Steven Douskey ,  Rudolf Haring ,  Steven Oakland ,  Michael Ouellette ,  Scott Strissel

IPC分类号： G11C29/00 ,  G11C7/00

CPC分类号： G11C29/4401 ,  G11C29/802

摘要： Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The method comprises the further step of, at a given time, passing the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

摘要翻译： 公开了一种修复包括多个存储器阵列的类型的集成电路的方法，以及用于控制用于控制阵列的冗余逻辑的控制数据的保险丝盒。 该方法包括以下步骤：向集成电路提供控制数据选择器，用于将控制数据从保险丝盒传送到存储器阵列; 提供备用控制数据源，集成电路外部; 并将替代控制数据源连接到控制数据选择器。 该方法还包括在给定时间，通过控制数据选择器将备用控制数据从其源传递到存储器阵列以控制存储器阵列的冗余逻辑的步骤。

公开(公告)号：US20070230260A1

公开(公告)日：2007-10-04

申请号：US11278238

申请日：2006-03-31

申请人： Kevin Gorman ,  Emory Keller ,  Michael Ouellette

发明人： Kevin Gorman ,  Emory Keller ,  Michael Ouellette

IPC分类号： G11C29/00 ,  G11C7/00

CPC分类号： G11C29/16 ,  G11C2029/5002

摘要： A Built-In-Self-Test (BIST) state machine providing BIST testing operations associated with a thermal sensor device(s) located in proximity to the circuit(s) to which BIST testing operations are applied. The thermal sensor device compares the current temperature value sensed to a predetermined temperature threshold and determines whether the predetermined threshold is exceeded. A BIST control element suspends the BIST testing operation in response to meeting or exceeding said predetermined temperature threshold, and initiates resumption of BIST testing operations when the current temperature value normalizes or is reduced. A BIST testing methodology implements steps for mitigating the exceeded temperature threshold condition in response to determining that the predetermined temperature threshold is met or exceeded. These steps include one of: ignoring the BIST results of the suspect circuit(s), or by causing the BIST state machine to enter a wait state and adjusting operating parameters of the suspect circuits while in the wait state.

摘要翻译： 内置自测试（BIST）状态机，提供与位于BIST测试操作所在电路附近的热传感器设备相关的BIST测试操作。 热传感器装置将感测到的当前温度值与预定温度阈值进行比较，并确定是否超过预定阈值。 BIST控制元件响应于满足或超过所述预定温度阈值而暂停BIST测试操作，并且当当前温度值归一化或降低时，启动BIST测试操作的恢复。 响应于确定满足或超过预定温度阈值，BIST测试方法实现了减轻超过温度阈值条件的步骤。 这些步骤包括：忽略可疑电路的BIST结果，或通过使BIST状态机进入等待状态，并在等待状态下调整可疑电路的工作参数。