公开(公告)号：US5120909A

公开(公告)日：1992-06-09

申请号：US692404

申请日：1991-04-26

申请人： David A. Kutz ,  Tod R. Earhart

发明人： David A. Kutz ,  Tod R. Earhart

IPC分类号： G06F13/40 ,  H04L12/40

CPC分类号： H04L12/40045 ,  G06F13/4086 ,  H04L12/40 ,  H04L25/0298

摘要： A circuit for detecting and verifying a presence of a terminating device for a high speed data transmission line. The circuit contains a first cable detector which generates a first signal if a first cable is present. A second cable detector generates a second signal if a second cable is present. The terminating device is contained in a plurality of resistor packs, each of the which contains an extra resistor. A terminating device detector senses the extra resistor presence, thereby detecting the presence of the resistor packs. The terminating device detector generates an ALL-EQUIPPED signal and a NON-EQUIPPED signal, the ALL-EQUIPPED signal is generated when all of the plurality of resistor packs are present, the NON-EQUIPPED signal is generated when all of the plurality of resistor packs are absent. Finally, a verifier circuit receives the first signal, the second signal, the ALL-EQUIPPED signal and the NON-EQUIPPED signal. The verifier circuit verifies that if the ALL-EQUIPPED signal is present then only one of the first signal or the second signal is present, or, if the NON-EQUIPPED signal is present both the first signal and the second signal are present.

摘要翻译： 一种用于检测和验证用于高速数据传输线的终端设备的存在的电路。 该电路包含第一电缆检测器，如果存在第一电缆，则产生第一信号。 如果存在第二缆线，则第二缆线检测器产生第二信号。 终端设备包含在多个电阻器组件中，每个电阻器组件包含一个额外的电阻器。 终端设备检测器检测额外的电阻器存在，从而检测电阻器组件的存在。 终端设备检测器产生ALL-EQUIPPED信号和NON-EQUIPPED信号，当所有多个电阻器组件都存在时，产生ALL-EQUIPPED信号，当所有多个电阻器组件全部产生时，产生NON-EQUIPPED信号 没有 最后，验证器电路接收第一信号，第二信号，ALL-EQUIPPED信号和NON-EQUIPPED信号。 验证器电路验证如果存在ALL-EQUIPPED信号，则仅存在第一信号或第二信号中的一个，或者如果存在第一信号和第二信号的非有效信号。

公开(公告)号：US4862076A

公开(公告)日：1989-08-29

申请号：US206983

申请日：1988-05-26

申请人： Robert E. Renner ,  David A. Kutz

发明人： Robert E. Renner ,  David A. Kutz

IPC分类号： G01R1/04

CPC分类号： G01R1/0416 ,  Y10S439/912

摘要： This arrangement provides for attaching test or probe leads for such instruments as a logic analyzer to a leaded chip carrier. This arrangement provides for terminating each chip carrier lead to a metallic post upon which a logic probe or other test apparatus may be mechanically attached to make electrical connection. Since leaded chip carriers have their contact leads closely spaced, this arrangement expands this distance between leads to a suitable distance for connecting test probes. In this manner, the semiconductor chip may be functionally tested as part of a circuit on a printed wiring card.

摘要翻译： 这种布置提供了将用于诸如逻辑分析仪的仪器的测试或探针引线附接到引线芯片载体。 这种布置提供了将每个芯片载体引线端接到金属柱上，逻辑探针或其它测试装置可以机械连接到金属柱上以进行电连接。 由于引线芯片载体具有紧密间隔的接触引线，所以这种布置将引线之间的距离扩展到适合的距离以连接测试探针。 以这种方式，半导体芯片可以作为印刷线路卡上的电路的一部分进行功能测试。