利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

5 条记录 (耗时 0.029 秒)

    Control of multiple functional units with parallel operation in a microcoded execution unit
    2.
    发明授权
    Control of multiple functional units with parallel operation in a microcoded execution unit 失效
    在微型执行单元中并行运行的多功能单元的控制

    公开(公告)号：US5067069A

    公开(公告)日：1991-11-19

    申请号：US306832

    申请日：1989-02-03

    申请人： Elaine H. Fite ,  Tryggve Fossum ,  William R. Grundmann ,  Francis X. McKeen ,  Ronald M. Salett

    发明人： Elaine H. Fite ,  Tryggve Fossum ,  William R. Grundmann ,  Francis X. McKeen ,  Ronald M. Salett

    IPC分类号： G06F9/30 ,  G06F9/38

    CPC分类号： G06F9/30167 ,  G06F9/30101 ,  G06F9/3836 ,  G06F9/3857 ,  G06F9/3863 ,  G06F9/3867 ,  G06F9/3885

    摘要： To increase the performance of a pipelined processor executing various classes of instructions, the classes of instructions are executed by respective functional units which are independently controlled and operated in parallel. The classes of instructions include integer instructions, floating point instructions, multiply instructions, and divide instructions. The integer unit, which also performs shift operations, is controlled by the microcode execution unit to handle the wide variety of integer and shift operations included in a complex, variable-length instruction set. The other functional units need only accept a control command to initiate the operation to be performed by the functional unit. The retiring of the results of the instructions need not be controlled by the microcode execution unit, but instead is delegated to a separate retire unit that services a result queue. When the microcode execution unit determines that a new operation is required, an entry is inserted into the result queue. The entry includes all the information needed by the retire unit to retire the result once the result is available from the respective functional unit. The retire unit services the result queue by reading a tag in the entry at the head of the queue to determine the functional unit that is to provide the result. Once the result is available and the destination specified by the entry is also available, the result is retired in accordance with the entry, and the entry is removed from the queue.

    Two-pin distributed ethernet bus architecture
    3.
    发明授权
    Two-pin distributed ethernet bus architecture 有权
    双引脚分布式以太网总线架构

    公开(公告)号：US6061737A

    公开(公告)日：2000-05-09

    申请号：US227800

    申请日：1999-01-08

    申请人： David B. Fite, Jr. ,  Elaine H. Fite ,  Ron Salett

    发明人： David B. Fite, Jr. ,  Elaine H. Fite ,  Ron Salett

    IPC分类号： G06F13/368 ,  G06F13/00 ,  H04L12/413 ,  H04L12/44 ,  H04L12/46 ,  H04B3/36

    CPC分类号： H04L12/44 ,  H04L12/4135 ,  H04L12/46

    摘要： An intermodule network bus architecture using only two bus wires to transmit data and module state information. A two-pin bus interface in each network module connected to the bus provides for a distributed arbitration procedure in the event that two or more modules are competing for bus access, and provides a coding scheme under which both data signals and collision announcements are transmitted from module to module through the two-wire bus. The architecture handles multiple distributed repeater modules, as well as other network components such as bridges and routers connected to the same bus. An important aspect of the invention is that multiple bus interfaces function as a distributed state machine, to handle the arbitration process and to provide a consistent framework for detecting and processing data signals and various types of collisions, including receive collisions detected on a single local module port, and transmit collisions involving activity on multiple local ports of one or more modules.

    摘要翻译： 一种模块化的网络总线结构，仅使用两条总线来传输数据和模块状态信息。 连接到总线的每个网络模块中的双引脚总线接口在两个或多个模块竞争总线访问的情况下提供分布式仲裁程序，并提供一种编码方案，在该编码方案下，数据信号和冲突通知都从 模块通过双线总线模块。 该架构处理多个分布式中继器模块，以及其他网络组件，如连接到同一总线的网桥和路由器。 本发明的一个重要方面是多个总线接口用作分布式状态机，以处理仲裁过程并提供用于检测和处理数据信号和各种类型的冲突的一致的框架，包括在单个本地模块上检测到的接收冲突 端口，并发送涉及在一个或多个模块的多个本地端口上的活动的冲突。

    Two-pin distributed ethernet bus architecture
    4.
    发明授权
    Two-pin distributed ethernet bus architecture 失效

    公开(公告)号：US5963719A

    公开(公告)日：1999-10-05

    申请号：US589512

    申请日：1996-01-22

    申请人： David B. Fite, Jr. ,  Elaine H. Fite ,  Ron Salett

    发明人： David B. Fite, Jr. ,  Elaine H. Fite ,  Ron Salett

    IPC分类号： G06F13/368 ,  G06F13/00 ,  H04L12/413 ,  H04L12/44 ,  H04L12/46

    CPC分类号： H04L12/44 ,  H04L12/4135 ,  H04L12/46

    摘要： An intermodule network bus architecture using only two bus wires to transmit data and module state information. A two-pin bus interface in each network module connected to the bus provides for a distributed arbitration procedure in the event that two or more modules are competing for bus access, and provides a coding scheme under which both data signals and collision announcements are transmitted from module to module through the two-wire bus. The architecture handles multiple distributed repeater modules, as well as other network components such as bridges and routers connected to the same bus. An important aspect of the invention is that multiple bus interfaces function as a distributed state machine, to handle the arbitration process and to provide a consistent framework for detecting and processing data signals and various types of collisions, including receive collisions detected on a single local module port, and transmit collisions involving activity on multiple local ports of one or more modules.