公开(公告)号：US5142631A

公开(公告)日：1992-08-25

申请号：US306773

申请日：1989-02-03

申请人： John E. Murray ,  Mark A. Firstenberg ,  David B. Fite ,  Michael M. McKeon ,  Wiliam R. Grundmann ,  David A. Webb, Jr. ,  Ronald M. Salett ,  Tryggve Fossum ,  Dwight P. Manley ,  Ricky C. Hetherington

发明人： John E. Murray ,  Mark A. Firstenberg ,  David B. Fite ,  Michael M. McKeon ,  Wiliam R. Grundmann ,  David A. Webb, Jr. ,  Ronald M. Salett ,  Tryggve Fossum ,  Dwight P. Manley ,  Ricky C. Hetherington

IPC分类号： G06F9/38

CPC分类号： G06F9/355 ,  G06F9/345 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3857

摘要： A method is provided for preprocessing multiple instructions prior to execution of such instructions in a digital computer having an instruction decoder, an instruction execution unit, and multiple general purpose registers which are read to produce memory addresses during the preprocessing. The method comprises: (1) avoiding the preprocessing of a current instruction to read a general purpose register to produce a memory address prior to the modification of the contents of that register by a preceding instruction by (a) generating a composite write mask having a bit set for each general purpose register whose contents are to be modified by at least one of a plurality of decoded by not-yet-executed instructions preceding the current instruction, and (b) stalling the preprocessing of the current instruction when a general purpose register to be read by the current instruction is a register having a bit set in the write mask, and/or (2) avoiding the preprocessing of a current instruction which modifies the contents of a general purpose register that is to be read by a preceding instruction by (a) generating a composite read mask having a bit set for each general purpose register to be read by at least one of a plurality of decoded but not-yet-executed instructions preceding the current instruction, and (b) stalling the preprocessing of the current instruction when a general purpose register whose contents are to be modified by the current instruction is a register having a bit set in the read mask.

公开(公告)号：US5142634A

公开(公告)日：1992-08-25

申请号：US306760

申请日：1989-02-03

申请人： David B. Fite ,  John E. Murray ,  Dwight P. Manley ,  Michael M. McKeon ,  Elaine H. Fite ,  Ronald M. Salett ,  Tryggve Fossum

发明人： David B. Fite ,  John E. Murray ,  Dwight P. Manley ,  Michael M. McKeon ,  Elaine H. Fite ,  Ronald M. Salett ,  Tryggve Fossum

IPC分类号： G06F9/38

CPC分类号： G06F9/3806 ,  G06F9/3844

摘要： A branch prediction is made by searching a cache memory for branch history information associated with a branch instruction. If associated information is not found in the cache, then the branch is predicted based on a predetermined branch bias for the branch instruction's opcode; otherwise, the branch is predicted based upon the associated information from the cache. The associated information in the cache preferably includes a length, displacement, and target address in addition to a prediction bit. If the cache includes associated information predicting that the branch will be taken, the target address from cache is used so long as the associated length and displacement match and the length and displacement for the branch instruction; otherwise, the target address must be computed.

公开(公告)号：US5113515A

公开(公告)日：1992-05-12

申请号：US306831

申请日：1989-02-03

申请人： David B. Fite ,  Ricky C. Hetherington ,  Michael M. McKeon ,  Dwight P. Manley ,  John E. Murray

发明人： David B. Fite ,  Ricky C. Hetherington ,  Michael M. McKeon ,  Dwight P. Manley ,  John E. Murray

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/30145 ,  G06F9/30149 ,  G06F9/3816

摘要： An instruction buffer of a high speed digital computer controls the flow of instruction stream to an instruction decoder. The buffer provides the decoder with nine bytes of sequential instruction stream. The instruction set used by the computer is of the variable length type, such that the decoder consumes a variable number of the instruction stream bytes, depending upon the type of instruction being decoded. As each instruction is consumed, a shifter removes the consumed bytes and repositions the remaining bytes into the lowest order positions. The byte positions left empty by the shifter are filled by instruction stream retrieved from one of a pair of prefetch buffers (IBEX, IBEX2) or from a virtual instruction cache. These prefetch buffers are arranged to hold the next two subsequent quadwords of instruction stream and provide the desired missing bytes. The IBEX prefetch buffer is filled from the instruction cache after being emptied, but prior to those particular bytes being requested to fill the instruction decoder. This two level prefetching allows the relatively slow process of cache access to be performed during noncritical time. The instruction decoder is not stalled, waiting for a cache refill, but can ordinarily obtain the desired bytes of instruction stream from the prefetch buffer.