公开(公告)号：US20070071155A1

公开(公告)日：2007-03-29

申请号：US11236834

申请日：2005-09-27

申请人： David Boerstler ,  Matthew Fernsler ,  Eskinder Hailu ,  Jieming Qi ,  Mack Riley

发明人： David Boerstler ,  Matthew Fernsler ,  Eskinder Hailu ,  Jieming Qi ,  Mack Riley

IPC分类号： H04B17/00 ,  H03D3/24

CPC分类号： G06F1/10 ,  H03L7/095

摘要： An information handling system including a frequency synthesizer lock detection system is disclosed that distributes a frequency synthesizer output signal across a distribution network to one or more receptor circuits. The distribution network may exhibit delay and other distortion that may cause the downstream signal arriving at the receptor circuit to lose frequency lock with both the frequency synthesizer output signal and a reference clock signal that controls the frequency of the synthesizer output signal. The lock detection system tests the downstream signal to determine if the downstream signal exhibits a lock with respect to the reference clock that determines the operating frequency of the frequency synthesizer. In this manner, lock of the downstream signal to the reference clock signal may be accurately assessed in one embodiment.

摘要翻译： 公开了一种包括频率合成器锁定检测系统的信息处理系统，其将分频网络上的频率合成器输出信号分配到一个或多个接收器电路。 分配网络可能表现出延迟和其他失真，这些失真可能导致下游信号到达接收器电路，同时使用频率合成器输出信号和控制合成器输出信号频率的参考时钟信号来失去频率锁定。 锁定检测系统测试下行信号以确定下游信号是否相对于确定频率合成器的工作频率的参考时钟呈现锁定。 以这种方式，可以在一个实施例中精确地评估下行信号到参考时钟信号的锁定。

公开(公告)号：US20070071154A1

公开(公告)日：2007-03-29

申请号：US11236658

申请日：2005-09-27

申请人： David Boerstler ,  Matthew Fernsler ,  Eskinder Hailu ,  Jieming Qi ,  Mack Riley

发明人： David Boerstler ,  Matthew Fernsler ,  Eskinder Hailu ,  Jieming Qi ,  Mack Riley

IPC分类号： H03D3/24

CPC分类号： H03L7/093 ,  H03L7/095

摘要： A frequency synthesizer lock detection system is disclosed that distributes a frequency synthesizer output signal across a distribution network to one or more receptor circuits. The distribution network may exhibit delay and other distortion that may cause the downstream signal arriving at the receptor circuit to lose frequency lock with both the frequency synthesizer output signal and a reference clock signal that controls the frequency of the synthesizer output signal. The lock detection system tests the downstream signal to determine if the downstream signal exhibits a lock with respect to the reference clock that determines the operating frequency of the frequency synthesizer. In this manner, lock of the downstream signal to the reference clock signal may be accurately assessed in one embodiment.

摘要翻译： 公开了一种频率合成器锁定检测系统，其将分频网络上的频率合成器输出信号分配到一个或多个接收器电路。 分配网络可能表现出延迟和其他失真，这些失真可能导致下游信号到达接收器电路，同时使用频率合成器输出信号和控制合成器输出信号频率的参考时钟信号来失去频率锁定。 锁定检测系统测试下行信号以确定下游信号是否相对于确定频率合成器的工作频率的参考时钟呈现锁定。 以这种方式，可以在一个实施例中精确地评估下行信号到参考时钟信号的锁定。

公开(公告)号：US20070081620A1

公开(公告)日：2007-04-12

申请号：US11245308

申请日：2005-10-06

申请人： Irene Beattie ,  Nathan Chelstrom ,  Matthew Fernsler ,  Mack Riley

发明人： Irene Beattie ,  Nathan Chelstrom ,  Matthew Fernsler ,  Mack Riley

IPC分类号： H03D3/24

CPC分类号： H03L7/06 ,  H03L7/10

摘要： An apparatus and method for using electrical fuses (eFuses) to store phase-locked loop (PLL) configuration data are provided. With the apparatus and method, a portion of the eFuses present in the integrated circuit are reserved for the PLL configuration data. Upon power up, a power up controller and eFuse controller direct the sensing and serial transfer of the data in the portion of eFuses to the PLL under the reference clock. When the transfer is complete, the power up controller directs the PLL logic to load the configuration data and start. The mechanism of the present invention allows manufacturing to tailor the PLL configuration on a given device based on the characteristics of that device and its intended usage. Thus, the same PLL may be used in the same or different architectures to perform different operations based on the configuration data passed into the PLL from the eFuses.

摘要翻译： 提供了使用电熔丝（eFuses）来存储锁相环（PLL）配置数据的装置和方法。 利用该装置和方法，集成电路中存在的eFus的一部分被保留用于PLL配置数据。 上电时，上电控制器和eFuse控制器将eFuse部分中的数据的感测和串行传输指引到参考时钟下的PLL。 传输完成后，上电控制器指示PLL逻辑来加载配置数据并启动。 本发明的机构允许制造基于该设备的特性及其预期用途来定制给定设备上的PLL配置。 因此，可以在相同或不同的架构中使用相同的PLL，以便根据从eFuses传入PLL的配置数据执行不同的操作。