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1.发明申请公开(公告)号：US20070081620A1
公开(公告)日：2007-04-12
申请号：US11245308
申请日：2005-10-06
申请人： Irene Beattie , Nathan Chelstrom , Matthew Fernsler , Mack Riley
发明人： Irene Beattie , Nathan Chelstrom , Matthew Fernsler , Mack Riley
IPC分类号： H03D3/24
摘要： An apparatus and method for using electrical fuses (eFuses) to store phase-locked loop (PLL) configuration data are provided. With the apparatus and method, a portion of the eFuses present in the integrated circuit are reserved for the PLL configuration data. Upon power up, a power up controller and eFuse controller direct the sensing and serial transfer of the data in the portion of eFuses to the PLL under the reference clock. When the transfer is complete, the power up controller directs the PLL logic to load the configuration data and start. The mechanism of the present invention allows manufacturing to tailor the PLL configuration on a given device based on the characteristics of that device and its intended usage. Thus, the same PLL may be used in the same or different architectures to perform different operations based on the configuration data passed into the PLL from the eFuses.
摘要翻译： 提供了使用电熔丝（eFuses）来存储锁相环（PLL）配置数据的装置和方法。 利用该装置和方法，集成电路中存在的eFus的一部分被保留用于PLL配置数据。 上电时，上电控制器和eFuse控制器将eFuse部分中的数据的感测和串行传输指引到参考时钟下的PLL。 传输完成后，上电控制器指示PLL逻辑来加载配置数据并启动。 本发明的机构允许制造基于该设备的特性及其预期用途来定制给定设备上的PLL配置。 因此，可以在相同或不同的架构中使用相同的PLL，以便根据从eFuses传入PLL的配置数据执行不同的操作。
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公开(公告)号：US20060107093A1
公开(公告)日：2006-05-18
申请号：US10981156
申请日：2004-11-04
申请人： Irene Beattie , Ingemar Holm , Mack Riley
发明人： Irene Beattie , Ingemar Holm , Mack Riley
IPC分类号： G06F11/00
CPC分类号： G11C29/802
摘要： A method, an apparatus and a computer program product are provided for the compression of array redundancy data. Array redundancy data can be lengthy and take up a lot of space on a processor. This invention provides an algorithm that can compress array redundancy data for storage, and decompress and reload the array redundancy data at power-on of the processor. This compression algorithm saves a lot of space on the processor, which enables the processor to save power during operation, and function more efficiently. This algorithm also skips defective array redundancy data, which can be detrimental to the processor.
摘要翻译： 提供了用于压缩阵列冗余数据的方法，装置和计算机程序产品。 阵列冗余数据可能很长，并占用了处理器上的大量空间。 本发明提供了一种可以压缩阵列冗余数据进行存储并在处理器上电时对阵列冗余数据进行解压缩和重新加载的算法。 这种压缩算法在处理器上节省了大量的空间，这使得处理器能够在运行期间节省功耗，并且更有效地起作用。 该算法还跳过有缺陷的阵列冗余数据，这可能对处理器有害。
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公开(公告)号：US07308598B2
公开(公告)日：2007-12-11
申请号：US10981156
申请日：2004-11-04
申请人： Irene Beattie , Ingemar Holm , Mack Riley
发明人： Irene Beattie , Ingemar Holm , Mack Riley
CPC分类号： G11C29/802
摘要： A method, an apparatus and a computer program product are provided for the compression of array redundancy data. Array redundancy data can be lengthy and take up a lot of space on a processor. This invention provides an algorithm that can compress array redundancy data for storage, and decompress and reload the array redundancy data at power-on of the processor. This compression algorithm saves a lot of space on the processor, which enables the processor to save power during operation, and function more efficiently. This algorithm also skips defective array redundancy data, which can be detrimental to the processor.
摘要翻译： 提供了用于压缩阵列冗余数据的方法，装置和计算机程序产品。 阵列冗余数据可能很长，并占用了处理器上的大量空间。 本发明提供了一种可以压缩阵列冗余数据进行存储并在处理器上电时对阵列冗余数据进行解压缩和重新加载的算法。 这种压缩算法在处理器上节省了大量的空间，这使得处理器能够在运行期间节省功耗，并且更有效地起作用。 该算法还跳过有缺陷的阵列冗余数据，这可能对处理器有害。
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4.发明授权公开(公告)号：US07562272B2
公开(公告)日：2009-07-14
申请号：US11245308
申请日：2005-10-06
IPC分类号： G01R31/28
摘要： An apparatus and method for using electrical fuses (eFuses) to store phase-locked loop (PLL) configuration data are provided. With the apparatus and method, a portion of the eFuses present in the integrated circuit are reserved for the PLL configuration data. Upon power up, a power up controller and eFuse controller direct the sensing and serial transfer of the data in the portion of eFuses to the PLL under the reference clock. When the transfer is complete, the power up controller directs the PLL logic to load the configuration data and start. The mechanism of the present invention allows manufacturing to tailor the PLL configuration on a given device based on the characteristics of that device and its intended usage. Thus, the same PLL may be used in the same or different architectures to perform different operations based on the configuration data passed into the PLL from the eFuses.
摘要翻译： 提供了使用电熔丝（eFuses）来存储锁相环（PLL）配置数据的装置和方法。 利用该装置和方法，集成电路中存在的eFus的一部分被保留用于PLL配置数据。 上电时，上电控制器和eFuse控制器将eFuse部分中的数据的感测和串行传输指引到参考时钟下的PLL。 传输完成后，上电控制器指示PLL逻辑来加载配置数据并启动。 本发明的机构允许制造基于该设备的特性及其预期用途来定制给定设备上的PLL配置。 因此，可以在相同或不同的架构中使用相同的PLL，以便根据从eFuses传入PLL的配置数据执行不同的操作。
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公开(公告)号：US5386505A
公开(公告)日：1995-01-31
申请号：US161210
申请日：1993-11-30
摘要： Apparatus and methods for selectively controlling by window the number of overlay planes, the number of overlay palettes, and the overlay/underlay plane masks in a graphics video display system. A logic/multiplex control translates overlay and underlay data patterns from a multiple plane VRAM (Video Random Access Memory), referenced to the graphics system frame buffer, into window specific patterns. The window related translation is conveyed to conventional RAMDACs (Random Access Memory Digital-to-Analog Converters) for raster scan synchronized digital-to-analog conversion. The translation as provided by the controller is responsive to data selectively and dynamically written into a random access memory, thus providing translation of overlay/underlay data into window distinct and selective overlay/underlay palette functions.
摘要翻译： 用于通过窗口选择性地控制图形视频显示系统中覆盖平面的数量，叠加调色板的数量以及覆盖/底层平面掩模的装置和方法。 逻辑/多路复用控制将参考图形系统帧缓冲器的多平面VRAM（视频随机存取存储器）的覆盖和底层数据模式转换为窗口特定模式。 窗口相关的翻译被传送到用于光栅扫描同步的数模转换的常规RAMDAC（随机存取存储器数模转换器）。 由控制器提供的转换响应于有选择地和动态地写入随机存取存储器中的数据，从而提供覆盖/底层数据到窗口不同和选择性覆盖/底层调色板功能的翻译。
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公开(公告)号：US07688930B2
公开(公告)日：2010-03-30
申请号：US12129123
申请日：2008-05-29
IPC分类号： H03D3/24
摘要： A mechanism for using electrical fuses (eFuses) to store phase-locked loop (PLL) configuration data are provided. With the mechanism, a portion of the eFuses present in the integrated circuit are reserved for the PLL configuration data. Upon power up, a power up controller and eFuse controller direct the sensing and serial transfer of the data in the portion of eFuses to the PLL under the reference clock. When the transfer is complete, the power up controller directs the PLL logic to load the configuration data and start. The mechanism of the present invention allows manufacturing to tailor the PLL configuration on a given device based on the characteristics of that device and its intended usage. Thus, the same PLL may be used in the same or different architectures to perform different operations based on the configuration data passed into the PLL from the eFuses.
摘要翻译： 提供了一种使用电气保险丝（eFuses）来存储锁相环（PLL）配置数据的机制。 利用该机制，集成电路中存在的一部分eFuses被保留用于PLL配置数据。 上电时，上电控制器和eFuse控制器将eFuse部分中的数据的感测和串行传输指引到参考时钟下的PLL。 传输完成后，上电控制器指示PLL逻辑来加载配置数据并启动。 本发明的机构允许制造基于该设备的特性及其预期用途来定制给定设备上的PLL配置。 因此，可以在相同或不同的架构中使用相同的PLL，以便根据从eFuses传入PLL的配置数据执行不同的操作。
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公开(公告)号：US20080225566A1
公开(公告)日：2008-09-18
申请号：US12129123
申请日：2008-05-29
摘要： A mechanism for using electrical fuses (eFuses) to store phase-locked loop (PLL) configuration data are provided. With the mechanism, a portion of the eFuses present in the integrated circuit are reserved for the PLL configuration data. Upon power up, a power up controller and eFuse controller direct the sensing and serial transfer of the data in the portion of eFuses to the PLL under the reference clock. When the transfer is complete, the power up controller directs the PLL logic to load the configuration data and start. The mechanism of the present invention allows manufacturing to tailor the PLL configuration on a given device based on the characteristics of that device and its intended usage. Thus, the same PLL may be used in the same or different architectures to perform different operations based on the configuration data passed into the PLL from the eFuses.
摘要翻译： 提供了一种使用电气保险丝（eFuses）来存储锁相环（PLL）配置数据的机制。 利用该机制，集成电路中存在的一部分eFuses被保留用于PLL配置数据。 上电时，上电控制器和eFuse控制器将eFuse部分中的数据的感测和串行传输指引到参考时钟下的PLL。 传输完成后，上电控制器指示PLL逻辑来加载配置数据并启动。 本发明的机构允许制造基于该设备的特性及其预期用途来定制给定设备上的PLL配置。 因此，可以在相同或不同的架构中使用相同的PLL，以便根据从eFuses传入PLL的配置数据执行不同的操作。
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