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公开(公告)号：US5255287A
公开(公告)日：1993-10-19
申请号：US723085
申请日：1991-06-28
CPC分类号： H04L25/08 , H04L25/4923
摘要： Transceiver apparatus includes a transmitter circuit constructed with either emitter coupled logic (ECL) circuitry or programmable array logic circuitry, and a receiver circuit constructed with ECL circuitry. The transmitter circuit encodes a binary data signal received for transmission as a three-level modified duobinary encoded data signal and the receiver circuit decodes the received three-level encoded data signal to provide a binary data signal corresponding to the data signal received at the transmitter circuit for transmission. Both the transmitter and receiver circuits include features enabling transmitting and receiving high data-rate data signals.
摘要翻译： 收发器装置包括由发射极耦合逻辑（ECL）电路或可编程阵列逻辑电路构成的发射机电路，以及由ECL电路构成的接收机电路。 发射机电路对作为三电平修正的二进制编码数据信号进行传输接收的二进制数据信号进行编码，并且接收机电路对接收到的三电平编码数据信号进行解码，以提供对应于在发射机电路接收的数据信号的二进制数据信号 用于传输。 发射机和接收机电路都包括能够发送和接收高数据速率数据信号的特征。
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公开(公告)号：US4972161A
公开(公告)日：1990-11-20
申请号：US372683
申请日：1989-06-28
申请人： David C. Davies , Donald G. Vonada
发明人： David C. Davies , Donald G. Vonada
IPC分类号： H04L7/033
CPC分类号： H04L7/033
摘要： In a serial data communications system, an embedded clock is recovered from a data signal by incrementally controlling the frequency (thus phase) of a voltage-controlled oscillator in response to the difference in phase between the incoming data signal and the clock oscillator output. A transition of the data signal is detected and used to initiate a control pulse which is terminated upon the next transition in the clock oscillator output. A reference pulse is also generated which has a width about equal to a half cycle of the clock. These pulses are used to generate the voltage control for the oscillator, so that the phase relationship varies to see an equilibrium where the pulses are of equal width and the transitions of the clock are at midpoint of potential transitions of the data signal. The control can tolerate relatively long periods where there is no transition of the data signal. The control circuitry includes a counter for counting transitions of the clock to inhibit another detect operation from starting until three transitions after one has begun.
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公开(公告)号：US07062578B2
公开(公告)日：2006-06-13
申请号：US09977413
申请日：2001-10-15
CPC分类号： G06F13/4027 , G06T1/60 , G06T5/20
摘要： A flexible, reconfigurable processing system architecture allows for the implementation of a variety of processing system configurations to be implemented on a single device, which is preferably a PCI bus add-in extension board with an attached daughter card attached and electrically connected thereto through a PCI Mezzanine type connector, and which is plugged into a personal computer PCI expansion slot. The architecture uses the PCI bus, for example, as the local CPU bus for an embedded processor, which not only allows for flexibility in system configuration but also allows PCI devices to be hidden from the host CPU to allow for proper system startup. The architecture further permits an embedded processing CPU to be re-booted when the secondary PCI bus host bus bridge fails to respond without affecting host CPU or other secondary PCI bus peripheral devices. The architecture provides a method of loading an embedded system CPU's local memory with operating system and diagnostic code without the use of ROM or FLASH memory. A system and method of reserving memory is also disclosed which utilizes a dummy or surrogate board with little of no functionality but which has a class code of a common device such as an Ethernet card. The primary system BIOS will read the class code and reserve memory based on the surrogate card. The driver of the non-standard card such as an embedded processor, can then use the memory space allocated to the surrogate card by the BIOS.
摘要翻译： 灵活的可重新配置的处理系统架构允许实现在单个设备上实施的各种处理系统配置，其优选地是PCI总线附加扩展板，附加的子卡通过PCI连接并与其电连接 夹层式连接器，并插入个人计算机PCI扩展槽。 该架构使用PCI总线作为嵌入式处理器的本地CPU总线，这不仅允许系统配置的灵活性，而且允许从主机CPU隐藏PCI设备以允许正确的系统启动。 当辅助PCI总线主机总线桥接器无法响应而不影响主机CPU或其他辅助PCI总线外围设备时，架构还允许重新引导嵌入式处理CPU。 该架构提供了一种使用操作系统和诊断代码加载嵌入式系统CPU本地存储器的方法，而无需使用ROM或FLASH存储器。 还公开了一种保留存储器的系统和方法，其利用具有很少功能但具有诸如以太网卡的公共设备的类代码的虚拟或替代板。 主系统BIOS将读取类代码，并根据代理卡预留内存。 非标准卡的驱动程序（如嵌入式处理器）可以使用由BIOS分配给替代卡的存储空间。
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公开(公告)号：US06308234B1
公开(公告)日：2001-10-23
申请号：US09030411
申请日：1998-02-25
IPC分类号： G06F1300
CPC分类号： G06F13/4027 , G06T1/60 , G06T5/20
摘要： A flexible, reconfigurable processing system architecture allows for the implementation of a variety of processing system configurations to be implemented on a single device, which is preferably a PCI bus add-in extension board with an attached daughter card attached and electrically connected thereto through a PCI Mezzanine type connector, and which is plugged into a personal computer PCI expansion slot. The architecture uses the PCI bus, for example, as the local CPU bus for an embedded processor, which not only allows for flexibility in system configuration but also allows PCI devices to be hidden from the host CPU to allow for proper system startup. The architecture further permits an embedded processing CPU to be re-booted when the secondary PCI bus host bus bridge fails to respond without affecting host CPU or other secondary PCI bus peripheral devices. The architecture provides a method of loading an embedded system CPU's local memory with operating system and diagnostic code without the use of ROM or FLASH memory. A system and method of reserving memory is also disclosed which utilizes a dummy or surrogate board with little of no functionality but which has a class code of a common device such as an Ethernet card. The primary system BIOS will read the class code and reserve memory based on the surrogate card. The driver of the non-standard card such as an embedded processor, can then use the memory space allocated to the surrogate card by the BIOS.
摘要翻译： 灵活的可重新配置的处理系统架构允许实现在单个设备上实施的各种处理系统配置，其优选地是PCI总线附加扩展板，附加的子卡通过PCI连接并与其电连接 夹层式连接器，并插入个人计算机PCI扩展槽。 该架构使用PCI总线作为嵌入式处理器的本地CPU总线，这不仅允许系统配置的灵活性，而且允许从主机CPU隐藏PCI设备以允许正确的系统启动。 当辅助PCI总线主机总线桥接器无法响应而不影响主机CPU或其他辅助PCI总线外围设备时，架构还允许重新引导嵌入式处理CPU。 该架构提供了一种使用操作系统和诊断代码加载嵌入式系统CPU本地存储器的方法，而无需使用ROM或FLASH存储器。 还公开了一种保留存储器的系统和方法，其利用具有很少功能但具有诸如以太网卡的公共设备的类代码的虚拟或替代板。 主系统BIOS将读取类代码，并根据代理卡预留内存。 非标准卡的驱动程序（如嵌入式处理器）可以使用由BIOS分配给替代卡的存储空间。
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公开(公告)号：US4075702A
公开(公告)日：1978-02-21
申请号：US666362
申请日：1976-03-12
申请人： David C. Davies
发明人： David C. Davies
CPC分类号： H03M11/00 , A45C15/00 , G06F15/0216 , H01H13/84
摘要： Several embodiments of an electronic calculating apparatus and wallet enclosure are described. The apparatus is provided with a side-located battery compartment for providing, in combination with the enclosure, a very convenient and useful, relatively thin assembly. The enclosure comprises two flap members. A first one of the flap members is adapted for supporting the apparatus. The other is adapted for folding over in facing relationship with the first. In each of the embodiments the first flap member is provided with an interior wall member. In one embodiment, the apparatus is separably inserted and supported in a pocket formed by the interior wall member. Keys which extend from the face of the apparatus for inserting numbers and the like project through keyholes provided in the interior wall member. In another embodiment, the apparatus is provided with engaging members which extend outwardly from the ends thereof. The members are provided for engaging corresponding slots in the interior wall member and supporting the apparatus from the exterior side thereof. In still another, and even more compact, embodiment, the first flap member is made a part of an electrical circuit in the calculating apparatus in that the interior wall member comprises a deformable substrate for supporting one of two switch contacts in each of a plurality of switch means in the apparatus. The covering flap member in each of the embodiments may also be used for conveniently holding note paper, credit cards, blank checks, or the like.
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公开(公告)号：US5304939A
公开(公告)日：1994-04-19
申请号：US723083
申请日：1991-06-28
申请人： David C. Davies
发明人： David C. Davies
IPC分类号： G01R19/04 , H03K5/1532 , H03K5/153 , H03K5/08
CPC分类号： H03K5/1532 , G01R19/04
摘要： A peak detector circuit employs a line receiver of the ECL type, with the analog input signal to be tracked as a receiver input. The other receiver input is connected to the circuit output. A capacitor connects the output node of the circuit to threshold reference voltage input. The capacitor is charged through a resistor from the output of the line receiver when the input signal exceeds the voltage on the output node, and the capacitor discharges to the reference input through this resistor and another resistor connecting the receiver output to the reference input. The output voltage tracks the peaks of the input signal. Oscillation of the receiver is avoided by using a threshold reference greater than zero. The dynamic range of the output can be extended to a level higher than that of ECL levels by summing the thresholds of a number of these detectors, using an operational amplifier.
摘要翻译： 峰值检测器电路采用ECL类型的线路接收器，模拟输入信号被跟踪为接收器输入。 另一个接收器输入连接到电路输出。 电容器将电路的输出节点连接到阈值参考电压输入。 当输入信号超过输出节点上的电压时，电容器通过电阻从线路接收器的输出充电，电容器通过该电阻放电到参考输入，另一个电阻将接收器输出连接到参考输入。 输出电压跟踪输入信号的峰值。 通过使用大于零的阈值参考来避免接收机的振荡。 使用运算放大器，可以将输出的动态范围扩展到高于ECL电平的电平，通过对多个这些检测器的阈值求和来实现。
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