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    Dual port programmable logic device variable depth and width memory array
    6.
    发明授权
    Dual port programmable logic device variable depth and width memory array 有权
    双端口可编程逻辑器件可变深度和宽度存储器阵列

    公开(公告)号：US06392954B2

    公开(公告)日：2002-05-21

    申请号：US09747191

    申请日：2000-12-21

    申请人： Srinivas T. Reddy ,  Christopher F. Lane ,  Manuel Mejia ,  Richard G. Cliff ,  Kerry Veenstra

    发明人： Srinivas T. Reddy ,  Christopher F. Lane ,  Manuel Mejia ,  Richard G. Cliff ,  Kerry Veenstra

    IPC分类号： G11C800

    CPC分类号： G11C7/1006

    摘要： A dual-port programmable logic device memory array is provided. Selectable-size data words may be written to and read from the array concurrently. Data is written into the array using write column decoder and data selection logic. The size of the data words handled by the write column decoder and data selection logic is controlled by mode select signals. Data is read from the array using read column decoder and data selection logic. The size of the data words handled by the read column decoder and data selection logic is also controlled by mode select signals. The write column decoder and data selection logic may be used to write data into the memory array at one selected location at the same time that the read column decoder and data selection logic is used to read data from the array at another selected location. A write row address decoder and a read row address decoder are used to independently address individual rows of memory cells in the memory array during writing and reading, respectively.

    摘要翻译： 提供了双端口可编程逻辑器件存储器阵列。 可选择大小的数据字可以并行写入阵列并从阵列中读取。 使用写列解码器和数据选择逻辑将数据写入阵列。 由写列解码器和数据选择逻辑处理的数据字的大小由模式选择信号控制。 使用读列解码器和数据选择逻辑从数组中读取数据。 由读列解码器和数据选择逻辑处理的数据字的大小也由模式选择信号控制。 写列解码器和数据选择逻辑可以用于在一个选定位置将数据写入存储器阵列，同时读列解码器和数据选择逻辑用于在另一选定位置从阵列中读取数据。 写入行地址解码器和读取行地址解码器分别用于在写入和读取期间独立地对存储器阵列中的存储单元的各行进行寻址。

    Dual-port programmable logic device variable depth and width memory array
    7.
    发明授权
    Dual-port programmable logic device variable depth and width memory array 失效
    双端口可编程逻辑器件可变深度和宽度存储器阵列

    公开(公告)号：US6052327A

    公开(公告)日：2000-04-18

    申请号：US107533

    申请日：1998-06-30

    申请人： Srinivas T. Reddy ,  Christopher F. Lane ,  Manuel Mejia ,  Richard G. Cliff ,  Kerry Veenstra

    发明人： Srinivas T. Reddy ,  Christopher F. Lane ,  Manuel Mejia ,  Richard G. Cliff ,  Kerry Veenstra

    IPC分类号： G11C11/41 ,  G11C7/10 ,  G11C8/00

    CPC分类号： G11C7/1006

    摘要： A dual-port programmable logic device memory array is provided. Selectable-size data words may be written to and read from the array concurrently. Data is written into the array using write column decoder and data selection logic. The size of the data words handled by the write column decoder and data selection logic is controlled by mode select signals. Data is read from the array using read column decoder and data selection logic. The size of the data words handled by the read column decoder and data selection logic is also controlled by mode select signals. The write column decoder and data selection logic may be used to write data into the memory array at one selected location at the same time that the read column decoder and data selection logic is used to read data from the array at another selected location. A write row address decoder and a read row address decoder are used to independently address individual rows of memory cells in the memory array during writing and reading, respectively.

    摘要翻译： 提供了双端口可编程逻辑器件存储器阵列。 可选择大小的数据字可以并行写入阵列并从阵列中读取。 使用写列解码器和数据选择逻辑将数据写入阵列。 由写列解码器和数据选择逻辑处理的数据字的大小由模式选择信号控制。 使用读列解码器和数据选择逻辑从数组中读取数据。 由读列解码器和数据选择逻辑处理的数据字的大小也由模式选择信号控制。 写列解码器和数据选择逻辑可以用于在一个选定位置将数据写入存储器阵列，同时读列解码器和数据选择逻辑用于在另一选定位置从阵列中读取数据。 写入行地址解码器和读取行地址解码器分别用于在写入和读取期间独立地对存储器阵列中的存储单元的各行进行寻址。

    Programmable logic device memory array circuit having combinable single-port memory arrays
    8.
    发明授权
    Programmable logic device memory array circuit having combinable single-port memory arrays 失效
    具有可组合单端口存储器阵列的可编程逻辑器件存储器阵列电路

    公开(公告)号：US06288970B1

    公开(公告)日：2001-09-11

    申请号：US09107926

    申请日：1998-06-30

    申请人： Srinivas T. Reddy ,  Christopher F. Lane ,  Manuel Mejia

    发明人： Srinivas T. Reddy ,  Christopher F. Lane ,  Manuel Mejia

    IPC分类号： G11C800

    CPC分类号： G11C7/1075 ,  G11C7/10 ,  G11C8/16 ,  G11C11/005

    摘要： A programmable logic device memory array circuit is provided that contains a pair of associated combinable single-port memory arrays. The memory array circuit may have a variable depth and width. The combinable single-port memory arrays may be operated independently if desired. Alternatively, a pair of the combinable single-port memory arrays can be combined to form a dual-port memory array. When the single-port memory arrays are combined to form a dual-port memory array, circuitry from a first of the combinable singleport memory arrays is used to perform writing operations and circuitry from a second of the combinable single-port memory arrays is used to perform reading operations. The availability of the dual-port memory array capability allows users to implement circuits such as first-in-first-out buffers and other circuits that require the ability to perform concurrent read and write operations. When such a dual-port capability is not required, two single-port memory arrays are available to implement a desired logic design.

    摘要翻译： 提供了一种可编程逻辑器件存储器阵列电路，其包含一对相关联的可组合单端口存储器阵列。 存储器阵列电路可以具有可变的深度和宽度。 如果需要，可组合的单端口存储器阵列可以独立地操作。 或者，一对可组合单端口存储器阵列可以组合以形成双端口存储器阵列。 当单端口存储器阵列组合以形成双端口存储器阵列时，来自第一可组合单端口存储器阵列的电路用于执行写入操作，并且来自第二可组合单端口存储器阵列的电路被用于 执行阅读操作。 双端口存储器阵列功能的可用性允许用户实现诸如先入先出缓冲器和需要执行并发读写操作的其他电路的电路。 当不需要这样的双端口功能时，两个单端口存储器阵列可用于实现期望的逻辑设计。

    Programmable logic device with redundant circuitry
    9.
    发明授权
    Programmable logic device with redundant circuitry 有权
    具有冗余电路的可编程逻辑器件

    公开(公告)号：US06344755B1

    公开(公告)日：2002-02-05

    申请号：US09691424

    申请日：2000-10-18

    申请人： Srinivas T. Reddy ,  Manuel Mejia ,  Andy L. Lee ,  Bruce B. Pedersen

    发明人： Srinivas T. Reddy ,  Manuel Mejia ,  Andy L. Lee ,  Bruce B. Pedersen

    IPC分类号： H03K19003

    CPC分类号： H03K19/17764 ,  H03K19/17736

    摘要： A programmable logic device is provided that allows a redundant row of programmable logic to be shifted into place to repair the device when a defect is detected in a row of programmable logic on the device. The redundant row is shifted into place by routing programming data into the normal logic and the redundant logic while bypassing the row of logic containing the defect. Switching circuitry may be used to direct programming data into the serial inputs of various data registers that are then used to load the programming data into the device. The patterns of programmable connections that are made between programmable logic regions on the device and vertical and horizontal conductors also allow redundant logic to be shifted into place. Some connections between the logic and the horizontal and vertical conductors may be identical within a column to facilitate shifting. Other connections may only partially overlap between respective rows. The partially overlapping pattern allows the connections to be less regular, which increases flexibility when routing signals on the device.

    摘要翻译： 提供了一种可编程逻辑器件，其允许在器件上的可编程逻辑行中检测到缺陷时将冗余的可编程逻辑行移位到位以修复器件。 通过将编程数据路由到正常逻辑和冗余逻辑中来绕过包含缺陷的逻辑行，将冗余行移位到位。 开关电路可用于将编程数据引导到各种数据寄存器的串行输入，然后将其用于将编程数据加载到器件中。 在设备上的可编程逻辑区域和垂直和水平导体之间进行的可编程连接的模式也允许将冗余逻辑移位到位。 逻辑和水平和垂直导体之间的一些连接可以在列内相同以便于移动。 其他连接可能仅在相应行之间部分重叠。 部分重叠的模式允许连接不太规则，这在设备上路由信号时增加灵活性。

    Programmable logic device memory array circuit having combinable single-port memory arrays
    10.
    发明授权
    Programmable logic device memory array circuit having combinable single-port memory arrays 有权
    具有可组合单端口存储器阵列的可编程逻辑器件存储器阵列电路

    公开(公告)号：US06191998B1

    公开(公告)日：2001-02-20

    申请号：US09452627

    申请日：1999-12-01

    申请人： Srinivas T. Reddy ,  Christopher F. Lane ,  Manuel Mejia

    发明人： Srinivas T. Reddy ,  Christopher F. Lane ,  Manuel Mejia

    IPC分类号： G11C800

    CPC分类号： G11C7/10 ,  G11C7/1075 ,  G11C8/16 ,  G11C11/005

    摘要： A programmable logic device memory array circuit is provided that contains a pair of associated combinable single-port memory arrays. The memory array circuit may have a variable depth and width. The combinable single-port memory arrays may be operated independently if desired. Alternatively, a pair of the combinable single-port memory arrays can be combined to form a dual-port memory array. When the single-port memory arrays are combined to form a dual-port memory array, circuitry from a first of the combinable single-port memory arrays is used to perform writing operations and circuitry from a second of the combinable single-port memory arrays is used to perform reading operations. The availability of the dual-port memory array capability allows users to implement circuits such as first-in-first-out buffers and other circuits that require the ability to perform concurrent read and write operations. When such a dual-port capability is not required, two single-port memory arrays are available to implement a desired logic design.

    摘要翻译： 提供了一种可编程逻辑器件存储器阵列电路，其包含一对相关联的可组合单端口存储器阵列。 存储器阵列电路可以具有可变的深度和宽度。 如果需要，可组合的单端口存储器阵列可以独立地操作。 或者，一对可组合单端口存储器阵列可以组合以形成双端口存储器阵列。 当单端口存储器阵列组合以形成双端口存储器阵列时，来自第一可组合单端口存储器阵列的电路用于执行写操作，并且来自第二可组合单端口存储器阵列的电路是 用于执行阅读操作。 双端口存储器阵列功能的可用性允许用户实现诸如先入先出缓冲器和需要执行并发读写操作的其他电路的电路。 当不需要这样的双端口功能时，两个单端口存储器阵列可用于实现期望的逻辑设计。