公开(公告)号：US06215326B1

公开(公告)日：2001-04-10

申请号：US09266235

申请日：1999-03-10

申请人： David E. Jefferson ,  Cameron McClintock ,  James Schleicher ,  Andy L. Lee ,  Manuel Mejia ,  Bruce B. Pedersen ,  Christopher F. Lane ,  Richard G. Cliff ,  Srinivas T. Reddy

发明人： David E. Jefferson ,  Cameron McClintock ,  James Schleicher ,  Andy L. Lee ,  Manuel Mejia ,  Bruce B. Pedersen ,  Christopher F. Lane ,  Richard G. Cliff ,  Srinivas T. Reddy

IPC分类号： H03K19177

CPC分类号： H03K19/1776 ,  H03K19/17736

摘要： A programmable logic device has a plurality of super-regions of programmable circuitry disposed on the device in a two-dimensional array of such super-regions. Each super-region includes a plurality of regions of programmable logic and a region of programmable memory. Each logic region includes a plurality of subregions of programmable logic. Each super-region has associated interconnection resources for allowing communication between the logic and memory regions of that super-region without the need to use, for such relatively local interconnections, the longer-length inter-super-region interconnection resources that are also provided on the device.

摘要翻译： 可编程逻辑器件具有设置在这种超区域的二维阵列中的设备上的多个可编程电路的超区域。 每个超区域包括可编程逻辑的多个区域和可编程存储器的区域。 每个逻辑区域包括可编程逻辑的多个子区域。 每个超区域具有相关联的互连资源，用于允许该超区域的逻辑和存储器区域之间的通信，而不需要为这样的相对局部互连使用也提供在较高长度的超超区域互连资源 装置。

公开(公告)号：US06879183B2

公开(公告)日：2005-04-12

申请号：US10260712

申请日：2002-09-27

申请人： David E. Jefferson ,  Cameron McClintock ,  James Schleicher ,  Andy L. Lee ,  Manuel Mejia ,  Bruce B. Pedersen ,  Christopher F. Lane ,  Richard G. Cliff ,  Srinivas T. Reddy

发明人： David E. Jefferson ,  Cameron McClintock ,  James Schleicher ,  Andy L. Lee ,  Manuel Mejia ,  Bruce B. Pedersen ,  Christopher F. Lane ,  Richard G. Cliff ,  Srinivas T. Reddy

IPC分类号： H01L21/82 ,  H03K19/173 ,  H03K19/177

CPC分类号： H03K19/1776 ,  H03K19/17736

摘要： A programmable logic device has a plurality of super-regions of programmable circuitry disposed on the device in a two-dimensional array of such super-regions. Each super-region includes a plurality of regions of programmable logic and a region of programmable memory. Each logic region includes a plurality of subregions of programmable logic. Each super-region has associated interconnection resources for allowing communication between the logic and memory regions of that super-region without the need to use, for such relatively local interconnections, the longer-length inter-super-region interconnection resources that are also provided on the device.

摘要翻译： 可编程逻辑器件具有设置在这种超区域的二维阵列中的设备上的多个可编程电路的超区域。 每个超区域包括可编程逻辑的多个区域和可编程存储器的区域。 每个逻辑区域包括可编程逻辑的多个子区域。 每个超区域具有相关联的互连资源，用于允许该超区域的逻辑和存储器区域之间的通信，而不需要为这样的相对局部互连使用也提供在较高长度的超超区域互连资源 装置。

公开(公告)号：US06480028B2

公开(公告)日：2002-11-12

申请号：US10062741

申请日：2002-02-01

申请人： David E. Jefferson ,  Cameron McClintock ,  James Schleicher ,  Andy L. Lee ,  Manuel Mejia ,  Bruce B. Pederson ,  Christopher F. Lane ,  Richard G. Cliff ,  Srinivas T. Reddy

发明人： David E. Jefferson ,  Cameron McClintock ,  James Schleicher ,  Andy L. Lee ,  Manuel Mejia ,  Bruce B. Pederson ,  Christopher F. Lane ,  Richard G. Cliff ,  Srinivas T. Reddy

IPC分类号： H03K19177

CPC分类号： H03K19/1776 ,  H03K19/17736

摘要： A programmable logic device has a plurality of super-regions of programmable circuitry disposed on the device in a two-dimensional array of such super-regions. Each super-region includes a plurality of regions of programmable logic and a region of programmable memory. Each logic region includes a plurality of subregions of programmable logic. Each super-region has associated interconnection resources for allowing communication between the logic and memory regions of that super-region without the need to use, for such relatively local interconnections, the longer-length inter-super-region interconnection resources that are also provided on the device.

摘要翻译： 可编程逻辑器件具有设置在这种超区域的二维阵列中的设备上的多个可编程电路的超区域。 每个超区域包括可编程逻辑的多个区域和可编程存储器的区域。 每个逻辑区域包括可编程逻辑的多个子区域。 每个超区域具有相关联的互连资源，用于允许该超区域的逻辑和存储器区域之间的通信，而不需要为这样的相对局部互连使用也提供在更高长度的超超区域互连资源 装置。

公开(公告)号：US06366121B2

公开(公告)日：2002-04-02

申请号：US09865227

申请日：2001-05-25

申请人： Richard G. Cliff ,  Francis B. Heile ,  Joseph Huang ,  Christopher F. Lane ,  Fung Fung Lee ,  Cameron McClintock ,  David W. Mendel ,  Ninh D. Ngo ,  Bruce B. Pedersen ,  Srinivas T. Reddy ,  Chiakang Sung ,  Kerry Veenstra ,  Bonnie I. Wang

发明人： Richard G. Cliff ,  Francis B. Heile ,  Joseph Huang ,  Christopher F. Lane ,  Fung Fung Lee ,  Cameron McClintock ,  David W. Mendel ,  Ninh D. Ngo ,  Bruce B. Pedersen ,  Srinivas T. Reddy ,  Chiakang Sung ,  Kerry Veenstra ,  Bonnie I. Wang

IPC分类号： G06F738

CPC分类号： H03K19/1736 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17744 ,  H03K19/1776

摘要： A programmable logic array integrated circuit device has a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of regions. The output signals of several regions share a group of drivers for applying region output signals to interconnection conductors that convey signals between regions. This conserves driver resources and increases signal routing flexibility. Various approaches can be used for configuring the interconnection conductors to also conserve interconnection conductor resources. Logic regions may be used to directly drive specific input/output cells, thereby simplifying signal routing to the I/O cells and also possibly simplifying the structure of the I/O cells (e.g., by allowing certain I/O cell functions to be performed in the associated logic region). Region output signal routing flexibility may also be enhanced to facilitate simultaneous performance of combinatorial logic and a separate “lonely register” function in modules of the regions.

摘要翻译： 可编程逻辑阵列集成电路器件具有多个可编程逻辑区域，该多个可编程逻辑区域以交叉行和列的区域的二维阵列布置在器件上。 几个区域的输出信号共享一组驱动器，用于将区域输出信号应用于在区域之间传送信号的互连导体。 这节省了驱动程序资源，并增加了信号路由的灵活性。 可以使用各种方法来配置互连导体，以便节省互连导体资源。 逻辑区域可以用于直接驱动特定的输入/输出单元，由此简化到I / O单元的信号路由，并且还可能简化I / O单元的结构（例如，通过允许执行某些I / O单元功能 在相关的逻辑区域）。 区域输出信号路由灵活性也可以被增强以促进组合逻辑的同时执行和区域模块中的单独的“孤独寄存器”功能。

公开(公告)号：US5909126A

公开(公告)日：1999-06-01

申请号：US672676

申请日：1996-06-28

申请人： Richard G. Cliff ,  Francis B. Heile ,  Joseph Huang ,  Christopher F. Lane ,  Fung Fung Lee ,  Cameron McClintock ,  David W. Mendel ,  Ninh D. Ngo ,  Bruce B. Pedersen ,  Srinivas T. Reddy ,  Chiakang Sung ,  Kerry Veenstra ,  Bonnie I. Wang

发明人： Richard G. Cliff ,  Francis B. Heile ,  Joseph Huang ,  Christopher F. Lane ,  Fung Fung Lee ,  Cameron McClintock ,  David W. Mendel ,  Ninh D. Ngo ,  Bruce B. Pedersen ,  Srinivas T. Reddy ,  Chiakang Sung ,  Kerry Veenstra ,  Bonnie I. Wang

IPC分类号： H03K19/04 ,  H03K19/177

CPC分类号： H03K19/17736 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17796 ,  H03K19/04

摘要： A programmable logic array integrated circuit device includes a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of such regions. Each row has a plurality of adjacent horizontal conductors, and each column has a plurality of adjacent vertical conductors. The regions in a row are interspersed with groups of local conductors which interconnect the adjacent regions and the associated horizontal and vertical conductors. The local conductors can also be used for intra-region communication, as well as communication between adjacent regions. Secondary signals such as clocks and clears for the regions can be drawn either from dedicated secondary signal conductors or normal region inputs. Memory cell requirements for region input signal selection are reduced by various techniques for sharing these memory cells.

摘要翻译： 可编程逻辑阵列集成电路器件包括以这种区域的交叉行和列的二维阵列布置在器件上的可编程逻辑的多个区域。 每行具有多个相邻的水平导体，并且每列具有多个相邻的垂直导体。 一排中的区域散布有互连相邻区域和相关联的水平和垂直导体的局部导体组。 本地导体也可用于区域内通信，以及相邻区域之间的通信。 辅助信号，例如时钟和区域的清除可以从专用辅助信号导体或正常区域输入中提取。 区域输入信号选择的存储单元要求通过用于共享这些存储单元的各种技术而减少。

公开(公告)号：US5963049A

公开(公告)日：1999-10-05

申请号：US807561

申请日：1997-02-28

申请人： Richard G. Cliff ,  Francis B. Heile ,  Joseph Huang ,  Christopher F. Lane ,  Fung Fung Lee ,  Cameron McClintock ,  David W. Mendel ,  Ninh D. Ngo ,  Bruce B. Pedersen ,  Srinivas T. Reddy ,  Chiakang Sung ,  Kerry Veenstra ,  Bonnie I. Wang

发明人： Richard G. Cliff ,  Francis B. Heile ,  Joseph Huang ,  Christopher F. Lane ,  Fung Fung Lee ,  Cameron McClintock ,  David W. Mendel ,  Ninh D. Ngo ,  Bruce B. Pedersen ,  Srinivas T. Reddy ,  Chiakang Sung ,  Kerry Veenstra ,  Bonnie I. Wang

IPC分类号： H03K19/173 ,  H03K19/177

CPC分类号： H03K19/1736 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17744 ,  H03K19/1776

摘要： A programmable logic array integrated circuit device has a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of regions. The output signals of several regions share a group of drivers for applying region output signals to interconnection conductors that convey signals between regions. This conserves driver resources and increases signal routing flexibility. Various approaches can be used for configuring the interconnection conductors to also conserve interconnection conductor resources. Logic regions may be used to directly drive specific input/output cells, thereby simplifying signal routing to the I/O cells and also possibly simplifying the structure of the I/O cells (e.g., by allowing certain I/O cell functions to be performed in the associated logic region). Region output signal routing flexibility may also be enhanced to facilitate simultaneous performance of combinatorial logic and a separate "lonely register" function in modules of the regions.

公开(公告)号：US5982195A

公开(公告)日：1999-11-09

申请号：US873169

申请日：1997-06-11

申请人： Richard G. Cliff ,  Francis B. Heile ,  Joseph Huang ,  Fung Fung Lee ,  Cameron McClintock ,  David W. Mendel ,  Bruce B. Pedersen ,  Srinivas T. Reddy ,  Chiakang Sung ,  Kerry Veenstra ,  Bonnie I. Wang

发明人： Richard G. Cliff ,  Francis B. Heile ,  Joseph Huang ,  Fung Fung Lee ,  Cameron McClintock ,  David W. Mendel ,  Bruce B. Pedersen ,  Srinivas T. Reddy ,  Chiakang Sung ,  Kerry Veenstra ,  Bonnie I. Wang

IPC分类号： H03K19/177 ,  H05K1/00 ,  H05K1/18

CPC分类号： H03K19/17736 ,  H03K19/17792 ,  H05K1/0286 ,  H05K1/181

摘要： A programmable logic device has regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of such regions. Horizontal interconnection conductors are associated with each row, and vertical interconnection conductors are associated with each column. Local conductors are interspersed between adjacent pairs of regions in each row for supplying signals to the regions on both sides of the local conductors. Subregions of programmable logic in each region generally have a local output and a global output. The global output is only usable to output to the relatively long-distance horizontal and vertical conductors. The local output is additionally usable as a local feedback and as a local connection to an adjacent region.

摘要翻译： 可编程逻辑器件具有以这种区域的交叉行和列的二维阵列设置在器件上的可编程逻辑区域。 水平互连导体与每行相关联，并且垂直互连导体与每列相关联。 局部导体分散在每一行的相邻区域对之间，用于向局部导体两侧的区域提供信号。 每个区域的可编程逻辑子区域通常具有本地输出和全局输出。 全局输出仅可用于输出到相对较长距离的水平和垂直导体。 本地输出可额外用作本地反馈和作为到相邻区域的本地连接。

公开(公告)号：US5847617A

公开(公告)日：1998-12-08

申请号：US909337

申请日：1997-08-11

申请人： Srinivas T. Reddy ,  David Edward Jefferson ,  Richard G. Cliff ,  Cameron McClintock

发明人： Srinivas T. Reddy ,  David Edward Jefferson ,  Richard G. Cliff ,  Cameron McClintock

IPC分类号： H03K3/03 ,  H03L7/099 ,  H03B5/24

CPC分类号： H03L7/0997 ,  H03K3/0315

摘要： A variable-path-length voltage-controlled oscillator circuit is provided. The oscillator circuit has a ring oscillator formed from a series of voltage-controlled inverter stages. The path length (i.e., the number of inverter stages) in the ring is selected based on path length configuration data stored in memory. The selected path length determines the nominal or center frequency of operation of the ring oscillator. The output frequency of the oscillator circuit is voltage-tuned about this center frequency by varying the delay of each inverter stage in the ring oscillator path. Various types of voltage-controlled inverter stages may be used, including current-starved inverter stages, variable-capacitive-load inverter stages, and differential-delay inverter stages. The voltage-controlled oscillator circuit may be used in a phase-locked loop on a programmable logic device for frequency synthesis or to eliminate clock skew.

摘要翻译： 提供了可变路径长度的压控振荡器电路。 振荡器电路具有由一系列压控逆变器级形成的环形振荡器。 基于存储在存储器中的路径长度配置数据来选择环路的路径长度（即，逆变器级数）。 所选择的路径长度决定了环形振荡器的额定或中心频率。 通过改变环形振荡器路径中每个反相器级的延迟，振荡器电路的输出频率就关于该中心频率进行电压调谐。 可以使用各种类型的压控变频器级，包括电流欠压级，可变容性负载逆变级和差分延迟逆变级。 压控振荡器电路可用于可编程逻辑器件上的锁相环，用于频率合成或消除时钟偏移。

公开(公告)号：US06661253B1

公开(公告)日：2003-12-09

申请号：US09931475

申请日：2001-08-16

申请人： Andy L. Lee ,  Wanli Chang ,  Cameron McClintock ,  John E. Turner ,  Brian D. Johnson ,  Chiao Kai Hwang ,  Richard Yen-Hsiang Chang ,  Richard G. Cliff

发明人： Andy L. Lee ,  Wanli Chang ,  Cameron McClintock ,  John E. Turner ,  Brian D. Johnson ,  Chiao Kai Hwang ,  Richard Yen-Hsiang Chang ,  Richard G. Cliff

IPC分类号： H03K19177

CPC分类号： H03K19/17736 ,  H03K17/063 ,  H03K19/177 ,  H03K19/1778

摘要： Enhanced passgate structures for use in low-voltage systems are presented in which the influence of Vt on the range of signals passed by single-transistor passgates is reduced. In one arrangement, the VGATE−Vt limit for signals propagated through NMOS passgates is raised by applying a higher VGATE; in another arrangement, the Vt is lowered. The use of CMOS passgates in applications where single-transistor passgates have traditionally been used is also presented.

公开(公告)号：US6034536A

公开(公告)日：2000-03-07

申请号：US982297

申请日：1997-12-01

申请人： Cameron McClintock ,  Andy L. Lee ,  Richard G. Cliff

发明人： Cameron McClintock ,  Andy L. Lee ,  Richard G. Cliff

IPC分类号： G06F11/20 ,  G11C29/00 ,  H03K19/177 ,  H03K19/003 ,  H03K19/173

CPC分类号： H03K19/17764 ,  G11C29/808 ,  H03K19/17728 ,  H03K19/17736

摘要： Redundant circuitry for a logic circuit such as a programmable logic device is provided. The redundant circuitry allows the logic circuit to be repaired by replacing a defective logic area on the circuit with a redundant logic circuit. Rows and columns of logic areas may be logically remapped by row and column swapping. The logic circuit contains dynamic control circuitry for directing programming data to various logic areas on the circuit in an order defined by redundancy configuration data. Redundancy may be implemented using either fully or partially redundant logic areas. Logic areas may be swapped to remap a partially redundant logic area onto a logic area containing a defect. The defect may then be repaired using row or column swapping or shifting. A logic circuit containing folded rows of logic areas may be repaired by replacing a defective half-row with a redundant half-row.