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    Ring oscillator-based Ising machine system
    3.
    发明授权
    Ring oscillator-based Ising machine system 有权

    公开(公告)号：US11545963B1

    公开(公告)日：2023-01-03

    申请号：US17540985

    申请日：2021-12-02

    申请人： Kenneth M. Zick

    发明人： Kenneth M. Zick

    IPC分类号： G06F17/11 ,  G06N7/00 ,  G06Q10/04 ,  H03K3/03 ,  H03K3/86

    摘要： One example includes an Ising machine system. The system includes a plurality of ring oscillators that are each configured to propagate an oscillation signal. Each of the ring oscillators can be cross-coupled with at least one other of the ring oscillators via a respective one of the oscillation signals to provide a respective phase coupling between the respective cross-coupled ring oscillators. The system also includes an Ising machine controller configured to generate control signals corresponding to parameters of an Ising problem and including a plurality of delay selection signals. The Ising machine controller can provide at least one of the delay selection signals to each of the ring oscillators. The delay selection signal can be configured to set a variable propagation delay of the ring oscillator to control the relative phase coupling of each of the ring oscillators to each of the at least one other of the ring oscillators.

    Speculative bus cycle acknowledge for 1/2X core/bus clocking
    4.
    发明授权
    Speculative bus cycle acknowledge for 1/2X core/bus clocking 失效
    1 / 2X内核/总线时钟的推测总线周期确认

    公开(公告)号：US6009533A

    公开(公告)日：1999-12-28

    申请号：US89275

    申请日：1998-06-02

    申请人： Kenneth M. Zick

    发明人： Kenneth M. Zick

    IPC分类号： G06F1/06 ,  G06F13/14

    CPC分类号： G06F13/1689 ,  G06F12/0831

    摘要： In a microprocessor, a speculative acknowledge/rescue scheme is implemented in the bus controller to increase bus cycle performance for 1/2X clocking. For the odd cycles of the bus controller clock that result from 1/2X clocking, bus cycle requests from the cache controller, which ordinarily cannot be acknowledged in the same bus controller clock as received (even though the bus cycle can still be run the that clock), are speculatively acknowledged. If the bus controller cannot run the bus cycle in that clock, rescue is initiated in which the bus cycle request is resubmitted in the next clock. In an exemplary embodiment, snoop write back requests are prioritized such that a pending rescue bus cycle will be stalled until the snoop write back request is completed. The speculative acknowledge/rescue scheme is advantageous in minimizing any adverse impact on performance by minimizing the number of unacknowledged bus cycle requests during odd clock cycles created by 1/2X clocking.

    摘要翻译： 在微处理器中，在总线控制器中实现了推测性的确认/救援方案，以增加+ E，1/2 + EE X时钟的总线周期性能。 对于总线控制器时钟的奇数周期，由+ E，1/2 + EE X时钟引起，来自高速缓存控制器的总线周期请求通常不能在接收到的同一总线控制器时钟中被确认（即使总线 循环仍然可以运行那个时钟），被推测认可。 如果总线控制器不能在该时钟内运行总线周期，则启动在下一个时钟内重新提交总线周期请求的救援。 在示例性实施例中，窥探回写请求被优先化，使得等待的救援总线周期将被停止，直到窥探回写请求完成。 推测性确认/救援方案有利于通过最小化由+ E，1/2 + EE X时钟创建的奇数时钟周期期间未确认的总线周期请求的数量来最小化对性能的任何不利影响。