公开(公告)号：US6150881A

公开(公告)日：2000-11-21

申请号：US317924

申请日：1999-05-25

申请人： David K. Lovelace ,  Danielle L. Coffing ,  Jeffery C. Durec

发明人： David K. Lovelace ,  Danielle L. Coffing ,  Jeffery C. Durec

IPC分类号： H03F3/45

CPC分类号： H03F3/45197 ,  H03F3/45085 ,  H03F3/45098 ,  H03F3/45502 ,  H03F2203/45418 ,  H03F2203/45458 ,  H03F2203/45471 ,  H03F2203/45702

摘要： A correction circuit (10) includes a transistor (30) that generates a feedback signal for equalizing the amplitude and adjusting the phase of the output signals (V.sub.OUT- and V.sub.OUT+) that are provided at the output of the variable gain amplifier (10). The base terminal of the transistor (30) receives a summed value of the output signals (V.sub.OUT- and V.sub.OUT+). The summed value is inverted and fed back to the differential transistors (12 and 14) and combined with the output signals (V.sub.OUT- and V.sub.OUT+). The output signals (V.sub.OUT- and V.sub.OUT+) have a proper amplitude and phase relationship when the summed value is substantially zero.

摘要翻译： 校正电路（10）包括晶体管（30），其产生用于均衡振幅并且调整在可变增益放大器（10）的输出处提供的输出信号（VOUT-和VOUT +）的相位的反馈信号。 晶体管（30）的基极端子接收输出信号（VOUT-和VOUT +）的相加值。 相加的值被反相并反馈到差分晶体管（12和14），并与输出信号（VOUT-和VOUT +）组合。 当总和值基本为零时，输出信号（VOUT-和VOUT +）具有适当的幅度和相位关系。

公开(公告)号：US6100763A

公开(公告)日：2000-08-08

申请号：US280600

申请日：1999-03-29

申请人： Jeffery C. Durec ,  David K. Lovelace ,  W. Eric Main

发明人： Jeffery C. Durec ,  David K. Lovelace ,  W. Eric Main

IPC分类号： H03F3/19 ,  H03G3/30 ,  H03F3/26

CPC分类号： H03F3/19 ,  H03F2200/372

摘要： An RF buffer (10) supplies a single ended output signal and differential output signals. An average voltage of the differential output signals is compared to a reference voltage (VR) by an amplifier (40). The amplifier (40) provides a feedback signal for controlling the bias current conducted by a first transistor (24) and a mirrored bias current conducted by a second transistor (46). The bias currents conducted by the first and second transistors (24, 46) are used to generate the differential output signals (OUT-, OUT+) and are substantially independent of the signal level at an input terminal (20). The signal current conducted by the first transistor (24) controls an output transistor (66), while the signal current conducted by the second transistor (46) controls another output transistor (56) in the push-pull output stage of the RF buffer (10).

摘要翻译： RF缓冲器（10）提供单端输出信号和差分输出信号。 通过放大器（40）将差分输出信号的平均电压与参考电压（VR）进行比较。 放大器（40）提供用于控制由第一晶体管（24）传导的偏置电流和由第二晶体管（46）传导的镜像偏置电流的反馈信号。 由第一和第二晶体管（24,46）传导的偏置电流用于产生差分输出信号（OUT-，OUT +），并且基本上与输入端子（20）处的信号电平无关。 由第一晶体管（24）传导的信号电流控制输出晶体管（66），而由第二晶体管（46）传导的信号电流控制RF缓冲器的推挽输出级中的另一个输出晶体管（56） 10）。

公开(公告)号：US6104227A

公开(公告)日：2000-08-15

申请号：US277867

申请日：1999-03-29

申请人： Jeffery C. Durec ,  David K. Lovelace ,  Dennis L. Welty

发明人： Jeffery C. Durec ,  David K. Lovelace ,  Dennis L. Welty

IPC分类号： H03D7/14 ,  G06F7/44

CPC分类号： H03D7/1433 ,  H03D7/1425 ,  H03D7/1441 ,  H03D7/145 ,  H03D7/1458 ,  H03D7/1491 ,  H03D2200/0025 ,  H03D2200/0043 ,  H03D2200/0084

摘要： An RF mixer (10) provides signal gain in a transconductor block (12). A first transistor (36) is sized M times larger than a second transistor (18) to generate the desired signal gain. The gain of the RF mixer (10) is the value M times an output impedance Z.sub.OUT divided by an input impedance Z.sub.IN. A first current (I.sub.40) conducted by the first transistor (36) is matched to a sum of the second current (I.sub.24) conducted by the second transistor (18) and a third current (I.sub.28). The first current is supplied to a first differential transistor pair (46, 48) and the summed current is supplied to a second differential transistor pair (56, 58) to provide balance in switching circuit (50).

摘要翻译： RF混频器（10）在跨导体块（12）中提供信号增益。 第一晶体管（36）的尺寸大于第二晶体管（18）的M倍，以产生期望的信号增益。 RF混频器（10）的增益是输出阻抗ZOUT除以输入阻抗ZIN的值M。 由第一晶体管（36）传导的第一电流（I40）与由第二晶体管（18）传导的第二电流（I24）和第三电流（I28）的和相匹配。 将第一电流提供给第一差分晶体管对（46,48），并将求和的电流提供给第二差分晶体管对（56,58），以在开关电路（50）中提供平衡。