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1.发明授权Amplifier circuit with amplitude and phase correction and method of operation 有权放大器电路具有幅度和相位校正和操作方法
公开(公告)号：US6150881A
公开(公告)日：2000-11-21
申请号：US317924
申请日：1999-05-25
IPC分类号： H03F3/45
CPC分类号： H03F3/45197 , H03F3/45085 , H03F3/45098 , H03F3/45502 , H03F2203/45418 , H03F2203/45458 , H03F2203/45471 , H03F2203/45702
摘要： A correction circuit (10) includes a transistor (30) that generates a feedback signal for equalizing the amplitude and adjusting the phase of the output signals (V.sub.OUT- and V.sub.OUT+) that are provided at the output of the variable gain amplifier (10). The base terminal of the transistor (30) receives a summed value of the output signals (V.sub.OUT- and V.sub.OUT+). The summed value is inverted and fed back to the differential transistors (12 and 14) and combined with the output signals (V.sub.OUT- and V.sub.OUT+). The output signals (V.sub.OUT- and V.sub.OUT+) have a proper amplitude and phase relationship when the summed value is substantially zero.
摘要翻译： 校正电路（10）包括晶体管（30），其产生用于均衡振幅并且调整在可变增益放大器（10）的输出处提供的输出信号（VOUT-和VOUT +）的相位的反馈信号。 晶体管（30）的基极端子接收输出信号（VOUT-和VOUT +）的相加值。 相加的值被反相并反馈到差分晶体管（12和14），并与输出信号（VOUT-和VOUT +）组合。 当总和值基本为零时，输出信号（VOUT-和VOUT +）具有适当的幅度和相位关系。
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2.发明授权Circuit and method of extending the linear range of a phase frequency detector 有权扩展相位频率检测器的线性范围的电路和方法
公开(公告)号：US6100721A
公开(公告)日：2000-08-08
申请号：US241669
申请日：1999-02-01
CPC分类号： G01R25/00 , H03D13/004 , H03L7/0891 , H03L7/10 , H04L2027/0067
摘要： A wireless communication system (10) uses a phase detector (28) having a first pair of flip-flops (50, 56) for detecting the phase difference between an input frequency and a reference frequency. The first pair of flip-flops control current sources (66, 70) in the charge pump of the phase detector to modulate the error signal. A second pair of flip-flops (52, 58) detect when the input frequency is more than 2.pi. ahead of or behind the reference frequency. The second pair of flip-flops increment and decrement a counter (54) which in turn controls additional current sources (78-88) in the charge pump. The additional current sources extend the linear operating range of the error signal when the phase error exceeds .+-.2.pi..
摘要翻译： 无线通信系统（10）使用具有用于检测输入频率和参考频率之间的相位差的第一对触发器（50,56）的相位检测器（28）。 第一对触发器控制相位检测器的电荷泵中的电流源（66,70），以调制误差信号。 第二对触发器（52,58）检测输入频率何时超过参考频率之前或之后的2π。 第二对触发器增加和减少计数器（54），反过来控制电荷泵中的附加电流源（78-88）。 当相位误差超过+/- 2 pi时，额外的电流源扩展了误差信号的线性工作范围。
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公开(公告)号：US5926052A
公开(公告)日：1999-07-20
申请号：US908827
申请日：1997-08-08
摘要： A circuit and method for producing a phase shifted quadrature signal (VOUT) from an in-phase signal (VIN). The in-phase signal (VIN) is applied to the control electrode of a voltage follower (121). The voltage follower (121) has a variable output resistance which combines with a capacitor (123) to delay the input signal (VIN) in accordance with the time constant formed by the variable output resistance and the capacitor (123). The variable output resistance is controlled by adjusting the bias current of the voltage follower (121) with a control signal.
摘要翻译： 用于从同相信号（VIN）产生相移正交信号（VOUT）的电路和方法。 同相信号（VIN）被施加到电压跟随器（121）的控制电极。 电压跟随器（121）具有可变输出电阻，其与电容器（123）组合以根据由可变输出电阻和电容器（123）形成的时间常数来延迟输入信号（VIN）。 通过用控制信号调节电压跟随器（121）的偏置电流来控制可变输出电阻。
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4.发明授权
公开(公告)号：US5578860A
公开(公告)日：1996-11-26
申请号：US431948
申请日：1995-05-01
申请人： Julio C. Costa , Wayne R. Burger , Natalino Camilleri , Christopher P. Dragon , Daniel J. Lamey , David K. Lovelace , David Q. Ngo
发明人： Julio C. Costa , Wayne R. Burger , Natalino Camilleri , Christopher P. Dragon , Daniel J. Lamey , David K. Lovelace , David Q. Ngo
IPC分类号： H01F17/00 , H01L21/822 , H01L21/8234 , H01L27/02 , H01L27/04 , H01L27/06 , H01L27/088 , H01L29/10 , H01L29/417 , H01L29/78 , H01L23/62 , H01L29/00 , H01L29/76
CPC分类号： H01L27/0251 , H01L27/0617 , H01L29/7835 , H01L29/1045 , H01L29/4175
摘要： A high frequency power FET device (22) is integrated with passive components (23,24,26,28,31), an electro-static discharge (ESD) device (27,127,227), and/or a logic structure (29) on a semiconductor body (13) to form a monolithic high frequency integrated circuit structure (10). The high frequency power FET device (22) includes a grounded source configuration. The logic structure (29) utilizes the high frequency power FET structure in a grounded source configuration as one device in a CMOS implementation.
摘要翻译： 高频功率FET器件（22）与无源元件（23,24,26,28,31），静电放电（ESD）器件（27,127,227）和/或逻辑结构（29）集成在一起 半导体本体（13），以形成单片高频集成电路结构（10）。 高频功率FET器件（22）包括接地源配置。 逻辑结构（29）利用接地源配置中的高频功率FET结构作为CMOS实现中的一个器件。
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5.发明授权Selective implementation of power management schemes based on detected computer operating environment 有权基于检测到的计算机操作环境选择性实施电源管理方案公开(公告)号：US07055047B2
公开(公告)日：2006-05-30
申请号：US10410089
申请日：2003-04-09
申请人： Klaas Wortel , David K. Lovelace , Luis J. Briones
发明人： Klaas Wortel , David K. Lovelace , Luis J. Briones
IPC分类号： G06F1/32
CPC分类号： G06F1/3215 , G06F1/3259 , Y02D10/155
摘要： Detecting a radio frequency (RF) environment around a computer and using a power management scheme for an RF user input device being used by the computer system. If the computer system is in a single user environment, a power management scheme may be used to conserve power on the RF user input device. If the computer system is in a multi-user environment, a power management scheme may be used to minimize interference between neighboring computer systems by minimizing the signal strength of the RF signal from the RF user input device and the RF signal from the computer system.
摘要翻译： 检测计算机周围的射频（RF）环境，并为计算机系统正在使用的RF用户输入设备使用电源管理方案。 如果计算机系统处于单个用户环境中，则可以使用电源管理方案来节省RF用户输入设备上的功率。 如果计算机系统处于多用户环境中，则可以使用功率管理方案来最小化来自RF用户输入设备的RF信号的信号强度和来自计算机系统的RF信号来最小化相邻计算机系统之间的干扰。
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公开(公告)号：US06819196B2
公开(公告)日：2004-11-16
申请号：US10366177
申请日：2003-02-13
申请人： David K. Lovelace , Klaas Wortel
发明人： David K. Lovelace , Klaas Wortel
IPC分类号： H03B532
摘要： An oscillator circuit. In one embodiment, the oscillator includes a gain circuit, an envelope detector, and an amplitude comparison circuit. The trans-conductance circuit is configured to amplify a periodic signal produced by a crystal. Amplitude peaks of the periodic signal may be detected in the envelope detector, which may determine an average amplitude value based on the detected peaks. The average amplitude value may be compared to a DC voltage value in an amplitude comparison circuit. The DC voltage value may include both a DC average of the periodic signal as well as a predetermined DC offset value. The gain circuit may adjust the level of amplification of the periodic signal based on a feedback signal in order to ensure that the oscillator produces a periodic output signal at a desired level so as to insure oscillation and the minimum use of current to achieve oscillations.
摘要翻译： 振荡电路。 在一个实施例中，振荡器包括增益电路，包络检测器和振幅比较电路。 跨导电路被配置为放大由晶体产生的周期信号。 可以在包络检测器中检测周期信号的幅度峰值，其可以基于检测到的峰值来确定平均振幅值。 平均振幅值可以与幅度比较电路中的直流电压值进行比较。 DC电压值可以包括周期信号的DC平均值以及预定的DC偏移值。 增益电路可以基于反馈信号来调节周期信号的放大电平，以便确保振荡器产生期望电平的周期性输出信号，从而确保振荡和电流的最小使用以实现振荡。
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公开(公告)号：US6133797A
公开(公告)日：2000-10-17
申请号：US363221
申请日：1999-07-30
申请人： David K. Lovelace , Jeffrey C. Durec , Mike McGinn , Klaas Wortel
发明人： David K. Lovelace , Jeffrey C. Durec , Mike McGinn , Klaas Wortel
CPC分类号： H03L7/099 , H03L7/0891 , H03L7/095 , H03L7/10
摘要： A PLL system (10) includes a PFD (24) that receives a reference clock signal (REF CLK) and a feedback clock signal (FBK CLK). The PFD (24) generates an analog signal (TUNE) based on the phase and frequency relationship of the reference and feedback clock signals. The PFD (24) also generates a clock signal based on two PI phase slips for clocking a counter (70). The analog signal is compared against an upper and lower reference voltage in a threshold detect circuit (34) and the signals UP and DOWN supplied to the counter (70). The counter (70) provides a count value that controls the resonant frequency generated by a tank circuit (73). The tuning range of an oscillator (18) is extended by changing the capacitance of the tank circuit (73).
摘要翻译： PLL系统（10）包括接收参考时钟信号（REF CLK）和反馈时钟信号（FBK CLK）的PFD（24）。 PFD（24）基于参考和反馈时钟信号的相位和频率关系产生模拟信号（TUNE）。 PFD（24）还基于用于对计数器（70）计时的两个PI相位差产生时钟信号。 将模拟信号与阈值检测电路（34）中的上限和下限参考电压以及提供给计数器（70）的信号UP和DOWN进行比较。 计数器（70）提供控制由电路（73）产生的谐振频率的计数值。 振荡器（18）的调谐范围通过改变储能电路（73）的电容来延长。
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公开(公告)号：US6100763A
公开(公告)日：2000-08-08
申请号：US280600
申请日：1999-03-29
CPC分类号： H03F3/19 , H03F2200/372
摘要： An RF buffer (10) supplies a single ended output signal and differential output signals. An average voltage of the differential output signals is compared to a reference voltage (VR) by an amplifier (40). The amplifier (40) provides a feedback signal for controlling the bias current conducted by a first transistor (24) and a mirrored bias current conducted by a second transistor (46). The bias currents conducted by the first and second transistors (24, 46) are used to generate the differential output signals (OUT-, OUT+) and are substantially independent of the signal level at an input terminal (20). The signal current conducted by the first transistor (24) controls an output transistor (66), while the signal current conducted by the second transistor (46) controls another output transistor (56) in the push-pull output stage of the RF buffer (10).
摘要翻译： RF缓冲器（10）提供单端输出信号和差分输出信号。 通过放大器（40）将差分输出信号的平均电压与参考电压（VR）进行比较。 放大器（40）提供用于控制由第一晶体管（24）传导的偏置电流和由第二晶体管（46）传导的镜像偏置电流的反馈信号。 由第一和第二晶体管（24,46）传导的偏置电流用于产生差分输出信号（OUT-，OUT +），并且基本上与输入端子（20）处的信号电平无关。 由第一晶体管（24）传导的信号电流控制输出晶体管（66），而由第二晶体管（46）传导的信号电流控制RF缓冲器的推挽输出级中的另一个输出晶体管（56） 10）。
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公开(公告)号：US5617056A
公开(公告)日：1997-04-01
申请号：US498038
申请日：1995-07-05
CPC分类号： G05F3/265
摘要： A base current compensation circuit (10) generates a current that tracks a gain of a transistor (11). The compensation circuit (10) includes a current mirror formed by a mirror transistor (12) and an output transistor (14). The mirror transistor (12) is connected to the transistor (11) whose gain is tracked. A current source (16) and a feedback transistor (13) causes the mirror transistor (12) to draw a base current from the transistor (11) so that a collector current of the transistor (11) matches a reference current. The output transistor (14) amplifies the base current of the transistor (11) to generate the tracking current in the collector electrode of the output transistor (14).
摘要翻译： 基极电流补偿电路（10）产生跟踪晶体管（11）的增益的电流。 补偿电路（10）包括由镜晶体管（12）和输出晶体管（14）形成的电流镜。 镜晶体管（12）连接到其增益被跟踪的晶体管（11）。 电流源（16）和反馈晶体管（13）使得反射镜晶体管（12）从晶体管（11）抽取基极电流，使得晶体管（11）的集电极电流与参考电流相匹配。 输出晶体管（14）放大晶体管（11）的基极电流，以在输出晶体管（14）的集电极中产生跟踪电流。
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公开(公告)号：US6104227A
公开(公告)日：2000-08-15
申请号：US277867
申请日：1999-03-29
CPC分类号： H03D7/1433 , H03D7/1425 , H03D7/1441 , H03D7/145 , H03D7/1458 , H03D7/1491 , H03D2200/0025 , H03D2200/0043 , H03D2200/0084
摘要： An RF mixer (10) provides signal gain in a transconductor block (12). A first transistor (36) is sized M times larger than a second transistor (18) to generate the desired signal gain. The gain of the RF mixer (10) is the value M times an output impedance Z.sub.OUT divided by an input impedance Z.sub.IN. A first current (I.sub.40) conducted by the first transistor (36) is matched to a sum of the second current (I.sub.24) conducted by the second transistor (18) and a third current (I.sub.28). The first current is supplied to a first differential transistor pair (46, 48) and the summed current is supplied to a second differential transistor pair (56, 58) to provide balance in switching circuit (50).
摘要翻译： RF混频器（10）在跨导体块（12）中提供信号增益。 第一晶体管（36）的尺寸大于第二晶体管（18）的M倍，以产生期望的信号增益。 RF混频器（10）的增益是输出阻抗ZOUT除以输入阻抗ZIN的值M。 由第一晶体管（36）传导的第一电流（I40）与由第二晶体管（18）传导的第二电流（I24）和第三电流（I28）的和相匹配。 将第一电流提供给第一差分晶体管对（46,48），并将求和的电流提供给第二差分晶体管对（56,58），以在开关电路（50）中提供平衡。
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