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公开(公告)号：US20050149706A1
公开(公告)日：2005-07-07
申请号：US11069771
申请日：2005-03-01
申请人： David Kruckemyer , Daniel Murray
发明人： David Kruckemyer , Daniel Murray
CPC分类号： G06F9/324 , G06F9/30054 , G06F9/3806
摘要： A link address/sequential address generation circuit is provided for generating a link/sequential address. The circuit receives the most significant bits of at least two addresses: a first address of a first set of bytes including a branch instruction and a second address of a second set of bytes contiguous to the first set. The least significant bits of the branch PC (those bits not included in the most significant bits of the addresses received by the circuit) are used to generate the least significant bits of the link/sequential address and to select one of the first address and the second address to supply the most significant bits.
摘要翻译： 提供链路地址/顺序地址生成电路用于生成链路/顺序地址。 该电路接收至少两个地址的最高有效位：包括分支指令的第一组字节的第一地址和与第一组相邻的第二组字节的第二地址。 分支PC的最低有效位（不包括在由电路接收的地址的最高有效位中的位）被用于生成链路/顺序地址的最低有效位，并且选择第一地址和 第二个地址提供最重要的位。
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公开(公告)号：US20050015577A1
公开(公告)日：2005-01-20
申请号：US10920766
申请日：2004-08-18
申请人： David Kruckemyer
发明人： David Kruckemyer
CPC分类号： G06F9/3842 , G06F9/3844 , G06F9/3859
摘要： A first tag is assigned to a branch instruction. Dependent on the type of branch instruction, a second tag is assigned to an instruction in the branch delay slot of the branch instruction. The second tag may equal the first tag if the branch delay slot is unconditional for that branch, and may equal a different tag if the branch delay slot is conditional for the branch. If the branch is mispredicted, the first tag is broadcast to pipeline stages that may have speculative instructions, and the first tag is compared to tags in the pipeline stages. If the tag in a pipeline stage matches the first tag, the instruction is not cancelled. If the tag mismatches, the instruction is cancelled.
摘要翻译： 第一个标签被分配给分支指令。 根据分支指令的类型，将第二标签分配给分支指令的分支延迟时隙中的指令。 如果分支延迟时隙对于该分支是无条件的，则第二标签可以等于第一标签，并且如果分支延迟时隙对于分支是有条件的，则可以等于不同的标签。 如果分支被错误预测，则将第一标签广播到可能具有推测性指令的流水线阶段，并且将第一标签与流水线阶段中的标签进行比较。 如果流水线阶段的标签与第一个标签匹配，则该指令不会被取消。 如果标签不匹配，则说明被取消。
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公开(公告)号：US20050132176A1
公开(公告)日：2005-06-16
申请号：US11046439
申请日：2005-01-28
申请人： David Kruckemyer
发明人： David Kruckemyer
CPC分类号： G06F9/3842
摘要： A first tag is assigned to a branch instruction. Dependent on the type of branch instruction, a second tag is assigned to an instruction in the branch delay slot of the branch instruction. If the branch is mispredicted, the first tag is broadcast to pipeline stages that may have speculative instructions, and the first tag is compared to tags in the pipeline stages to determine which instructions to cancel. The assignment of tags for a fetch group of concurrently fetched instructions may be performed in parallel. A plurality of branch sequence numbers may be generated, and one of the plurality may be selected for each instruction responsive to the cumulative number of branch instructions preceding that instruction within the fetch group. The selection may be further responsive to whether or not the instruction is in a conditional delay slot.
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4.发明申请Distributed Cache Coherence at Scalable Requestor Filter Pipes that Accumulate Invalidation Acknowledgements from other Requestor Filter Pipes Using Ordering Messages from Central Snoop Tag 有权可扩展请求者的分布式缓存一致性累积无效的过滤器来自其他请求者过滤器管道的致谢使用来自中央监听标签的订购消息公开(公告)号：US20070186054A1
公开(公告)日：2007-08-09
申请号：US11307413
申请日：2006-02-06
IPC分类号： G06F13/28
CPC分类号： G06F12/082 , G06F12/0828
摘要： A multi-processor, multi-cache system has filter pipes that store entries for request messages sent to a central coherency controller. The central coherency controller orders requests from filter pipes using coherency rules but does not track completion of invalidations. The central coherency controller reads snoop tags to identify sharing caches having a copy of a requested cache line. The central coherency controller sends an ordering message to the requesting filter pipe. The ordering message has an invalidate count indicating the number of sharing caches. Each sharing cache receives an invalidation message from the central coherency controller, invalidates its copy of the cache line, and sends an invalidation acknowledgement message to the requesting filter pipe. The requesting filter pipe decrements the invalidate count until all sharing caches have acknowledged invalidation. All ordering, data, and invalidation acknowledgement messages must be received by the requesting filter pipe before loading the data into its cache.
摘要翻译： 多处理器，多缓存系统具有过滤器管道，其存储发送到中央一致性控制器的请求消息的条目。 中央一致性控制器使用一致性规则对来自过滤器管道的请求进行排序，但不跟踪完成无效。 中央一致性控制器读取窥探标签以识别具有所请求的高速缓存行的副本的共享高速缓存。 中央一致性控制器向请求过滤管发送排序消息。 排序消息具有指示共享缓存数量的无效计数。 每个共享缓存从中央一致性控制器接收到无效消息，使其高速缓存行的副本无效，并向请求的过滤器管道发送无效确认消息。 请求过滤管道减少无效计数，直到所有共享缓存都确认无效。 在将数据加载到其缓存中之前，请求过滤器管道必须接收所有排序，数据和无效确认消息。
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5.发明申请公开(公告)号：US20050149698A1
公开(公告)日：2005-07-07
申请号：US11069375
申请日：2005-03-01
CPC分类号： G06F9/3836 , G06F9/3838 , G06F9/3857 , G06F9/3859 , G06F9/3863
摘要： An apparatus for a processor includes a first scoreboard, a second scoreboard, and a control circuit coupled to the first scoreboard and the second scoreboard. The control circuit is configured to update the first scoreboard to indicate that a write is pending for a first destination register of a first instruction in response to issuing the first instruction into a first pipeline. The control circuit is configured to update the second scoreboard to indicate that the write is pending for the first destination register in response to the first instruction passing a first stage of the pipeline. Replay may be signaled for a given instruction at the first stage. In response to a replay of a second instruction, the control circuit is configured to copy a contents of the second scoreboard to the first scoreboard. In various embodiments, additional scoreboards may be used for detecting different types of dependencies.
摘要翻译： 用于处理器的装置包括第一记分板，第二记分板和耦合到第一记分板和第二记分板的控制电路。 控制电路被配置为响应于将第一指令发布到第一管道中而更新第一记分板以指示针对第一指令的第一目的地寄存器的等待写入。 控制电路被配置为响应于通过流水线的第一级的第一指令，更新第二记分板以指示该第一目的地寄存器的写暂停。 在第一阶段可能会发出给定指令的重播信号。 响应于第二指令的重放，控制电路被配置为将第二记分板的内容复制到第一记分板。 在各种实施例中，附加记分板可用于检测不同类型的依赖性。
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