公开(公告)号：US5740181A

公开(公告)日：1998-04-14

申请号：US662403

申请日：1996-06-12

申请人： Craig A. Heikes ,  Glenn T. Colon-Bonet ,  David R. Smentek ,  Robert H. Miller, Jr.

发明人： Craig A. Heikes ,  Glenn T. Colon-Bonet ,  David R. Smentek ,  Robert H. Miller, Jr.

IPC分类号： G01R31/3185 ,  G06F11/00

CPC分类号： G01R31/318522

摘要： The operation of a pipeline is observed by launching two or more sets of data into the pipeline on consecutive clock cycles. The clock free-runs for as many cycles as it takes the data to propagate through the stages of the pipeline. The output latches of each stage of the pipeline are only sampled when the data of interest is held in each output latch, respectively. Observation may be completely controlled through a standard test access port (TAP). Observation may be accomplished by halting the clock to scan new data in and results out, or with the clock free-running. The inputs to the pipeline may come from test registers or from circuitry which feeds the pipeline during normal operation.

摘要翻译： 通过在连续的时钟周期内将两组或更多组数据发送到流水线来观察流水线的操作。 时钟自由运行，因为它需要数据传播通过管道的阶段。 只有当感兴趣的数据分别保存在每个输出锁存器中时，才会对流水线的每一级的输出锁存器进行采样。 观察可以通过标准测试访问端口（TAP）完全控制。 观察可以通过暂停时钟来扫描新数据并导出，或者与时钟自由运行来实现。 管道的输入可能来自测试寄存器或来自在正常操作期间馈送流水线的电路。

公开(公告)号：US5740087A

公开(公告)日：1998-04-14

申请号：US656125

申请日：1996-05-31

申请人： David R. Smentek ,  Craig A. Heikes ,  Robert H. Miller, Jr.

发明人： David R. Smentek ,  Craig A. Heikes ,  Robert H. Miller, Jr.

IPC分类号： G06F1/32 ,  G06F9/38 ,  G06F1/00

CPC分类号： G06F9/3836 ,  G06F1/3203 ,  G06F1/3287 ,  G06F9/3867 ,  G06F9/3869 ,  Y02B60/1282

摘要： An apparatus and method are disclosed for regulating power consumption in a digital system of the kind including at least one triggerable functional block that consumes more power when triggered than when not triggered. In an embodiment for use with a digital system that includes a pipeline of such triggerable functional blocks, a state machine sequentially applies trigger pulses to each of the functional blocks in the pipeline whenever the output of an OR gate is asserted. It does so by generating a series of enable signals that are used to gate a clock signal to the trigger inputs of the functional blocks. The state machine includes a series of storage devices having outputs. Outputs of the storage devices are used to provide the enable signals. The inputs of the OR gate are coupled to a start signal that indicates when the functional blocks should be triggered to process data, and also to a dummy start signal that indicates when the functional blocks should be triggered to maintain power consumption. Outputs from the storage devices are also used to indicate the number of times the pipeline has been triggered during a recent number of clock cycles. A programmable register is used to store a data value corresponding to the minimum desired level of power consumption for the pipelined functional blocks. The dummy start signal is generated by combinational logic whose inputs include the outputs of the storage devices and the data value. Because the minimum desired level of power consumption may be programmed by the user, thermal characterization and balancing of step load with average power are facilitated.

摘要翻译： 公开了一种用于调节这种类型的数字系统中的功率消耗的装置和方法，包括当触发时比不触发时消耗更多功率的至少一个可触发功能块。 在包括这种可触发的功能块的流水线的数字系统的一个实施例中，状态机在每个OR门的输出被断言的情况下，在流水线中的每个功能块上顺序地施加触发脉冲。 它通过产生用于将时钟信号门控到功能块的触发输入的一系列使能信号来实现。 状态机包括具有输出的一系列存储装置。 存储设备的输出用于提供使能信号。 或门的输入耦合到起始信号，该启动信号指示何时触发功能块以处理数据，以及指示何时触发功能块以维持功耗的虚拟启动信号。 来自存储设备的输出也用于指示在最近数量的时钟周期期间流水线被触发的次数。 可编程寄存器用于存储对应于流水线功能块的最小期望功耗水平的数据值。 虚拟启动信号由组合逻辑产生，其输入包括存储设备的输出和数据值。 由于用户可以编程所需的最小功耗水平，因此易于平均功率的步进负载的热表征和平衡。

公开(公告)号：US5557620A

公开(公告)日：1996-09-17

申请号：US533415

申请日：1995-09-25

申请人： Robert H. Miller, Jr. ,  Craig A. Heikes

发明人： Robert H. Miller, Jr. ,  Craig A. Heikes

IPC分类号： G01R31/26 ,  G01R31/30 ,  G01R31/317 ,  H01L21/66 ,  G06F11/00

CPC分类号： G01R31/3004

摘要： A system and method for quiescent current testing of dynamic logic circuitry. Nodes shorted to ground are detected during a dynamic pre-charge state. Nodes shorted to a power supply potential are detected by driving all nodes of interest to ground during a dynamic evaluation phase. Nodes of interest are driven to ground directly by one additional transistor per node or indirectly by logical propagation from upstream nodes. As a result, only two current measurements are needed for all shorted node faults, even for pipelined systems with multiple clocks. There is no need for input test signal sequences and no need for signal propagation to outputs for detection. Specific embodiments are provided for single-rail logic, single-rail pipelined systems, dual-rail logic and dual-rail pipelined systems. For single-rail pipelined systems, optional transistors between stages enable preservation of logical states during testing. For dual-rail logic, storage nodes and static nodes are forced to a logical state that is not possible during normal operation. For pipelined dual-rail logic, testing of alternate stages inherently preserves the logical state of the system during testing.

摘要翻译： 一种静态电流测试动态逻辑电路的系统和方法。 在动态预充电状态期间检测到接地短路的节点。 通过在动态评估阶段将感兴趣的所有节点驱动到地面来检测短路到电源电位的节点。 感兴趣的节点通过每个节点的一个附加晶体管直接驱动到地，或间接通过来自上游节点的逻辑传播。 因此，即使对于具有多个时钟的流水线系统，所有短路节点故障都只需要两个电流测量。 不需要输入测试信号序列，不​​需要信号传播到输出进行检测。 为单轨逻辑，单轨流水线系统，双轨逻辑和双轨流水线系统提供具体实施例。 对于单轨流水线系统，阶段之间的可选晶体管能够在测试期间保持逻辑状态。 对于双轨逻辑，存储节点和静态节点被强制为在正常操作期间不可能的逻辑状态。 对于流水线双轨逻辑，替代阶段的测试固有地保留系统在测试期间的逻辑状态。

公开(公告)号：US5343096A

公开(公告)日：1994-08-30

申请号：US885584

申请日：1992-05-19

申请人： Craig A. Heikes ,  Robert H. Miller, Jr.

发明人： Craig A. Heikes ,  Robert H. Miller, Jr.

IPC分类号： G11C11/409 ,  G01R31/30 ,  H03K19/003 ,  H03K19/096

CPC分类号： H03K19/00384 ,  G01R31/30 ,  H03K19/096

摘要： The present invention tolerates the decay of a dynamic logic circuit by preserving the logic state of the output before the decay. A slow clock detector is configured to detect a slow clock condition of the clock pertaining to the dynamic logic circuit. A tolerant storage device is configured to preserve the data output by command of the slow clock detector upon a detection of the slow clock condition.

摘要翻译： 本发明通过在衰减之前保持输出的逻辑状态来容忍动态逻辑电路的衰减。 慢时钟检测器被配置为检测与动态逻辑电路相关的时钟的慢时钟条件。 容忍存储装置被配置为在检测到慢时钟条件时保留由慢时钟检测器的命令输出的数据。

公开(公告)号：US5798938A

公开(公告)日：1998-08-25

申请号：US677432

申请日：1996-07-02

申请人： Craig A. Heikes ,  Rodolfo G. Beraha

发明人： Craig A. Heikes ,  Rodolfo G. Beraha

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： The present invention provides a system and method for performing precharge timing verification on a logic circuit comprising a plurality of cascaded logic blocks, where in each logic block is implemented via a dynamic logic gate characterized by having a clock resettable output. In addition, a storage element is connected at each input to the logic circuit. The method of the present invention includes the following steps: preconditioning the storage elements so that all the inputs to the logic circuit are driven high when the clock goes high; transitioning the clock high so as to drive all the inputs of the logic circuit high, thereby driving all the outputs of the logic circuit high and discharging the storage node of each logic block; transitioning the clock low to precharge the storage node of all the logic blocks in the logic circuit, and thereby driving all the outputs low; and determining the longest precharge path in the logic circuit. A precharged timing verification system of the present invention is preferably implemented on a computer system and comprises a dynamic simulation mechanism and a precharge timing mechanism for performing the precharge timing verification timing analysis of the present invention.

摘要翻译： 本发明提供了一种用于在包括多个级联逻辑块的逻辑电路上执行预充电定时验证的系统和方法，其中在每个逻辑块中经由动态逻辑门来实现，其特征在于具有时钟可复位输出。 此外，存储元件在每个输入处连接到逻辑电路。 本发明的方法包括以下步骤：对存储元件进行预处理，使得当时钟变高时逻辑电路的所有输入被驱动为高电平; 将时钟转换为高电平，以将逻辑电路的所有输入驱动为高电平，从而驱动逻辑电路的所有输出为高电平，并对每个逻辑块的存储节点进行放电; 将时钟转换为低电平以对逻辑电路中的所有逻辑块的存储节点进行预充电，从而将所有输出驱动为低电平; 并确定逻辑电路中最长的预充电路径。 本发明的预充电定时验证系统优选地在计算机系统上实现，并且包括用于执行本发明的预充电定时验证定时分析的动态模拟机构和预充电定时机构。

公开(公告)号：US5268855A

公开(公告)日：1993-12-07

申请号：US944566

申请日：1992-09-14

申请人： Russell W. Mason ,  Craig A. Heikes

发明人： Russell W. Mason ,  Craig A. Heikes

IPC分类号： G06F7/57 ,  G06F7/38

CPC分类号： G06F7/483 ,  G06F9/30014 ,  G06F2207/3816

摘要： A technique for encoding multiple floating point formats into a double precision floating point number by padding single word floating point numbers with zeros to form a 64-bit double word in a way that allows a single precision arithmetic logic unit to be built on top of a double precision arithmetic logic unit. The formatting circuitry of the invention requires only small differences in the hardware for single and double precision operations so as to simplify the arithmetic logic unit and the multiplier of the floating point processing units. The encoding technique of the invention includes right justifying the exponent and mantissa of the floating point number in a "common format" such that rounding of the mantissa need only occur in one place, thereby greatly simplifying the rounding procedure. The technique of the invention also removes multiplexers from critical speed paths in the floating point processing units when it is desired to accommodate multiple data formats.

摘要翻译： 一种将多个浮点格式编码为双精度浮点数的技术，通过以零的方式填充单字浮点数以形成64位双字，以允许单精度算术逻辑单元构建在 双精度算术逻辑单元。 本发明的格式化电路在单精度和双精度运算的硬件上仅需要较小的差异，从而简化了浮点处理单元的算术逻辑单元和乘法器。 本发明的编码技术包括以“通用格式”对浮点数的指数和尾数进行右对齐，使得尾数的舍入仅需要在一个位置发生，从而大大简化舍入过程。 当希望容纳多种数据格式时，本发明的技术还可以从浮点处理单元中的临界速度路径中去除复用器。