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公开(公告)号：US5740181A
公开(公告)日：1998-04-14
申请号：US662403
申请日：1996-06-12
IPC分类号： G01R31/3185 , G06F11/00
CPC分类号： G01R31/318522
摘要： The operation of a pipeline is observed by launching two or more sets of data into the pipeline on consecutive clock cycles. The clock free-runs for as many cycles as it takes the data to propagate through the stages of the pipeline. The output latches of each stage of the pipeline are only sampled when the data of interest is held in each output latch, respectively. Observation may be completely controlled through a standard test access port (TAP). Observation may be accomplished by halting the clock to scan new data in and results out, or with the clock free-running. The inputs to the pipeline may come from test registers or from circuitry which feeds the pipeline during normal operation.
摘要翻译： 通过在连续的时钟周期内将两组或更多组数据发送到流水线来观察流水线的操作。 时钟自由运行，因为它需要数据传播通过管道的阶段。 只有当感兴趣的数据分别保存在每个输出锁存器中时，才会对流水线的每一级的输出锁存器进行采样。 观察可以通过标准测试访问端口（TAP）完全控制。 观察可以通过暂停时钟来扫描新数据并导出，或者与时钟自由运行来实现。 管道的输入可能来自测试寄存器或来自在正常操作期间馈送流水线的电路。
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2.发明授权
公开(公告)号：US5740087A
公开(公告)日：1998-04-14
申请号：US656125
申请日：1996-05-31
CPC分类号： G06F9/3836 , G06F1/3203 , G06F1/3287 , G06F9/3867 , G06F9/3869 , Y02B60/1282
摘要： An apparatus and method are disclosed for regulating power consumption in a digital system of the kind including at least one triggerable functional block that consumes more power when triggered than when not triggered. In an embodiment for use with a digital system that includes a pipeline of such triggerable functional blocks, a state machine sequentially applies trigger pulses to each of the functional blocks in the pipeline whenever the output of an OR gate is asserted. It does so by generating a series of enable signals that are used to gate a clock signal to the trigger inputs of the functional blocks. The state machine includes a series of storage devices having outputs. Outputs of the storage devices are used to provide the enable signals. The inputs of the OR gate are coupled to a start signal that indicates when the functional blocks should be triggered to process data, and also to a dummy start signal that indicates when the functional blocks should be triggered to maintain power consumption. Outputs from the storage devices are also used to indicate the number of times the pipeline has been triggered during a recent number of clock cycles. A programmable register is used to store a data value corresponding to the minimum desired level of power consumption for the pipelined functional blocks. The dummy start signal is generated by combinational logic whose inputs include the outputs of the storage devices and the data value. Because the minimum desired level of power consumption may be programmed by the user, thermal characterization and balancing of step load with average power are facilitated.
摘要翻译： 公开了一种用于调节这种类型的数字系统中的功率消耗的装置和方法，包括当触发时比不触发时消耗更多功率的至少一个可触发功能块。 在包括这种可触发的功能块的流水线的数字系统的一个实施例中，状态机在每个OR门的输出被断言的情况下，在流水线中的每个功能块上顺序地施加触发脉冲。 它通过产生用于将时钟信号门控到功能块的触发输入的一系列使能信号来实现。 状态机包括具有输出的一系列存储装置。 存储设备的输出用于提供使能信号。 或门的输入耦合到起始信号，该启动信号指示何时触发功能块以处理数据，以及指示何时触发功能块以维持功耗的虚拟启动信号。 来自存储设备的输出也用于指示在最近数量的时钟周期期间流水线被触发的次数。 可编程寄存器用于存储对应于流水线功能块的最小期望功耗水平的数据值。 虚拟启动信号由组合逻辑产生，其输入包括存储设备的输出和数据值。 由于用户可以编程所需的最小功耗水平，因此易于平均功率的步进负载的热表征和平衡。
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3.发明授权Method of decoupling the high order portion of the addend from the multiply result in an FMAC 失效将加法的高阶部分与乘法结果解耦的方法在FMAC中
公开(公告)号：US5757686A
公开(公告)日：1998-05-26
申请号：US566415
申请日：1995-11-30
CPC分类号： G06F7/5443 , G06F7/483 , G06F7/49936
摘要： A method and apparatus for decoupling the high order portion of the addend from the multiply result in an FMAC (floating-point multiply accumulate unit) such that the FMAC's datapath width is bounded to "2m+1"-bits, and the maximum width of required adders, shifters and leading bit anticipators is also bounded to "2m+1"-bits. The method and apparatus 1) reduce the necessary chip area for implementing an FMAC, and 2) reduce the length of routing paths through adders and shifters.
摘要翻译： 用于将加法的高阶部分与乘法结果相结合的方法和装置在FMAC（浮点乘法累加单元）中，使得FMAC的数据路径宽度被限制为“2m + 1”比特，并且最大宽度 所需的加法器，移位器和前导位预测器也限于“2m + 1”位。 该方法和装置1）减少用于实现FMAC的必要的芯片面积，以及2）通过加法器和移位器减少路由路径的长度。
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