Flexible control and status architecture for optical modules
    1.
    发明申请
    Flexible control and status architecture for optical modules 失效
    灵活的光模块控制和状态架构

    公开(公告)号:US20050286902A1

    公开(公告)日:2005-12-29

    申请号:US11167410

    申请日:2005-06-27

    IPC分类号: H04B10/00 H04B10/24

    CPC分类号: H04B10/40

    摘要: The invention relates to optoelectronic modules for generating and/or receiving optical signals for use in fiber-optic communication systems, such as optical transponders or transceivers, having a reconfigurable control and status (C&S) interface with a host device. The optoelectronic module includes an electrical multi-pin host connector having a plurality of pins for communicating a plurality of digital C&S signals between the host and the module, functional hardware responsive to the digital control signals and comprising sensing means for generating digital status signals, and processing means formed by an FPGA and a processor for processing the digital C&S signals. The FPGA is disposed in communications paths between the host connector on one side, and the functional hardware and the processor on the other side, and programmed for routing each of the discrete C&S signals between the C&S pins of the host connector and the processor, and between the C&S pins and the functional hardware, thereby providing reconfigurability of said routing by downloading a different set of FPGA instructions.

    摘要翻译: 本发明涉及用于生成和/或接收用于光纤通信系统(例如光转发器或收发器)的光信号的光电子模块,其具有与主机设备的可重新配置的控制和状态(C&S)接口。 光电子模块包括具有用于在主机和模块之间传送多个数字C&S信号的多个引脚的电多针主机连接器,响应于数字控制信号的功能硬件,并且包括用于产生数字状态信号的感测装置,以及 处理装置由FPGA和用于处理数字C&S信号的处理器形成。 FPGA设置在一侧的主机连接器与另一侧的功能硬件和处理器之间的通信路径中,并被编程用于在主机连接器的C&S引脚和处理器之间路由每个分立的C&S信号,以及 在C&S引脚和功能硬件之间,从而通过下载不同的FPGA指令集来提供所述路由的可重新配置。

    MEMS control system gain normalization
    2.
    发明申请
    MEMS control system gain normalization 失效
    MEMS控制系统获得正常化

    公开(公告)号:US20070268553A1

    公开(公告)日:2007-11-22

    申请号:US11437026

    申请日:2006-05-19

    IPC分类号: G02B26/00

    摘要: A method and system for providing gain normalization in a MEMS control system and/or device includes moving a MEMS structure from a first position wherein light is redirected from a first input port to an output port to a second position wherein light is redirected from a second input port to the output port, dithering an orientation of the MEMS structure, monitoring an intensity of the dithered light and providing a feedback signal in dependence upon the monitored intensity, and using the feedback signal, determining a control loop gain for active alignment of the MEMS structure. Gain normalization is achieved by applying a fitting function, which is split into a gain control loop gain part and a mechanical part.

    摘要翻译: 用于在MEMS控制系统和/或设备中提供增益归一化的方法和系统包括将MEMS结构从第一位置移动,其中光从第一输入端口重定向到输出端口到第二位置,其中光从第二位置重定向 输入端口到输出端口,抖动MEMS结构的取向,监测抖动光的强度并根据所监测的强度提供反馈信号,并且使用反馈信号,确定用于主动对准的控制环增益 MEMS结构。 通过应用拟合功能实现增益归一化,该拟合功能分为增益控制环增益部分和机械部分。

    MEMS control system gain normalization
    3.
    发明授权
    MEMS control system gain normalization 失效
    MEMS控制系统获得正常化

    公开(公告)号:US07612931B2

    公开(公告)日:2009-11-03

    申请号:US11437026

    申请日:2006-05-19

    IPC分类号: G02B26/00

    摘要: A method and system for providing gain normalization in a MEMS control system and/or device includes moving a MEMS structure from a first position wherein light is redirected from a first input port to an output port to a second position wherein light is redirected from a second input port to the output port, dithering an orientation of the MEMS structure, monitoring an intensity of the dithered light and providing a feedback signal in dependence upon the monitored intensity, and using the feedback signal, determining a control loop gain for active alignment of the MEMS structure. Gain normalization is achieved by applying a fitting function, which is split into a gain control loop gain part and a mechanical part.

    摘要翻译: 用于在MEMS控制系统和/或设备中提供增益归一化的方法和系统包括将MEMS结构从第一位置移动,其中光从第一输入端口重定向到输出端口到第二位置,其中光从第二位置重定向 输入端口到输出端口,抖动MEMS结构的取向,监测抖动光的强度并根据所监测的强度提供反馈信号,并且使用反馈信号,确定用于主动对准的控制环增益 MEMS结构。 通过应用拟合功能实现增益归一化,该拟合功能分为增益控制环增益部分和机械部分。

    Flexible control and status architecture for optical modules
    4.
    发明授权
    Flexible control and status architecture for optical modules 失效
    灵活的光模块控制和状态架构

    公开(公告)号:US07466922B2

    公开(公告)日:2008-12-16

    申请号:US11167410

    申请日:2005-06-27

    IPC分类号: H04B10/04 H04B10/06

    CPC分类号: H04B10/40

    摘要: The invention relates to optoelectronic modules for generating and/or receiving optical signals for use in fiber-optic communication systems, such as optical transponders or transceivers, having a reconfigurable control and status (C&S) interface with a host device. The optoelectronic module includes an electrical multi-pin host connector having a plurality of pins for communicating a plurality of digital C&S signals between the host and the module, functional hardware responsive to the digital control signals and comprising sensing means for generating digital status signals, and processing means formed by an FPGA and a processor for processing the digital C&S signals. The FPGA is disposed in communications paths between the host connector on one side, and the functional hardware and the processor on the other side, and programmed for routing each of the discrete C&S signals between the C&S pins of the host connector and the processor, and between the C&S pins and the functional hardware, thereby providing reconfigurability of said routing by downloading a different set of FPGA instructions.

    摘要翻译: 本发明涉及用于生成和/或接收用于光纤通信系统(例如光转发器或收发器)的光信号的光电子模块,其具有与主机设备的可重新配置的控制和状态(C&S)接口。 光电子模块包括具有用于在主机和模块之间传送多个数字C&S信号的多个引脚的电多针主机连接器,响应于数字控制信号的功能硬件,并且包括用于产生数字状态信号的感测装置,以及 处理装置由FPGA和用于处理数字C&S信号的处理器形成。 FPGA设置在一侧的主机连接器与另一侧的功能硬件和处理器之间的通信路径中,并被编程用于在主机连接器的C&S引脚和处理器之间路由每个分立的C&S信号,以及 在C&S引脚和功能硬件之间,从而通过下载不同的FPGA指令集来提供所述路由的可重新配置。