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19 条记录 (耗时 0.043 秒)

    Method to prevent data loss in an electrically erasable read only memory
    4.
    发明授权
    Method to prevent data loss in an electrically erasable read only memory 失效
    防止电可擦除只读存储器中的数据丢失的方法

    公开(公告)号：US5596713A

    公开(公告)日：1997-01-21

    申请号：US478363

    申请日：1995-06-07

    申请人： David T. DeRoo ,  Mark D. Nicol ,  David J. DeLisle ,  Saifuddin Fakhruddin ,  Lloyd W. Gauthier ,  Robert A. Kohtz

    发明人： David T. DeRoo ,  Mark D. Nicol ,  David J. DeLisle ,  Saifuddin Fakhruddin ,  Lloyd W. Gauthier ,  Robert A. Kohtz

    IPC分类号： G06F1/00 ,  G06F9/30 ,  G06F9/32 ,  G06F9/445 ,  G06F9/50 ,  G06F11/00 ,  G06F12/14 ,  G06F21/00 ,  G11C29/00

    CPC分类号： G06F9/4401 ,  G06F11/004 ,  G06F12/1433 ,  G06F21/79 ,  G06F9/30101 ,  G06F9/30141 ,  G06F9/32 ,  G06F9/5016 ,  G11C29/88

    摘要： An apparatus and method for tracking and interception of instructions as they are presented to the memory, selectively passing harmless data to the device and disallowing the sequences which instruct the device to perform harmful functions, such as self-erase. A software trap is provided to be transparent to the operation of the device and the host system, imposing no harmful timing delays or software overhead. Accordingly, the invention allows the use of standard electrically erasable read-only memories in an application which requires that the device be protected from global erasure. A hardware front end intercepts the software command which is used to globally erase the device. The apparatus receives address signals from the computer system corresponding to the protected peripheral device, receives data signals from the computer system to the protected peripheral device, tracks a predetermined sequence of address and address signals, substitutes at least one of the data signals received with a replacement data signal, and sends a replacement data signal.

    摘要翻译： 一种用于在将指令呈现给存储器时跟踪和截取指令的设备和方法，选择性地将无害数据传送到设备，并且禁止指示设备执行有害功能（例如自擦除）的序列。 提供软件陷阱对设备和主机系统的操作是透明的，不会产生有害的定时延迟或软件开销。 因此，本发明允许在需要保护设备免受全局擦除的应用中使用标准的电可擦除只读存储器。 硬件前端拦截用于全局擦除设备的软件命令。 该装置从对应于受保护的外围设备的计算机系统接收地址信号，从计算机系统接收数据信号到受保护的外围设备，跟踪预定的地址和地址信号序列，代替接收到的数据信号中的至少一个 替换数据信号，并发送替换数据信号。

    Multiprocessor system for enabling shared access to a memory
    5.
    发明授权
    Multiprocessor system for enabling shared access to a memory 失效
    用于启用对存储器的共享访问的多处理器系统

    公开(公告)号：US06161162A

    公开(公告)日：2000-12-12

    申请号：US480047

    申请日：1995-06-06

    申请人： David T. DeRoo ,  Mark D. Nicol ,  David J. DeLisle ,  Richard D. Ball ,  Saifuddin Fakhruddin ,  Lloyd W. Gauthier ,  Robert A. Kohtz ,  Jimmy D. Smith

    发明人： David T. DeRoo ,  Mark D. Nicol ,  David J. DeLisle ,  Richard D. Ball ,  Saifuddin Fakhruddin ,  Lloyd W. Gauthier ,  Robert A. Kohtz ,  Jimmy D. Smith

    IPC分类号： G06F1/00 ,  G06F9/30 ,  G06F9/445 ,  G06F12/14 ,  G06F21/00 ,  G06F13/18

    CPC分类号： G06F21/79 ,  G06F9/30101 ,  G06F9/4401 ,  G06F12/1433 ,  G06F2211/1097

    摘要： A multiprocessing computer system and method providing multiplexed address and data paths from multiple CPUs to a single storage device. These paths are controlled by an arbitration circuit which allows one CPU to always have the highest priority. The primary CPU may or may not be the highest priority CPU in the arbitration scheme. The arbitration circuit is combined with a controlling mechanism which interfaces to the memory device. This controller operates at a clock rate fast enough to allow the highest priority CPU to access the memory at it's highest data rate and, yet, guarantees a maximum idle period for the lower priority CPU to wait for it's interleaved memory access to complete. A single memory device provides cost and space savings. A controller is responsive to these processors to multiplex their information signals for selectively conveying information present at their address and data ports. A common memory device is addressable by the processors, and responsive to the controller to share addressing of the common memory device.

    摘要翻译： 一种多处理计算机系统和方法，其将多个地址和数据路径从多个CPU提供给单个存储设备。 这些路径由仲裁电路控制，仲裁电路允许一个CPU始终具有最高优先级。 主CPU可能是也可能不是仲裁方案中最高优先级的CPU。 仲裁电路与与存储器件接口的控制机构组合。 该控制器的时钟速率足够快，允许最高优先级的CPU以最高数据速率访问存储器，而且保证较低优先级CPU等待其交错存储器访问完成的最大空闲时间。 单个存储器件节省了成本和空间。 控制器响应于这些处理器来复用其信息信号，以选择性地传送存在于其地址和数据端口的信息。 公共存储器件可由处理器寻址，并响应于控制器共享公用存储器件的寻址。

    Protected address range in an electrically erasable programmable read only memory
    6.
    发明授权
    Protected address range in an electrically erasable programmable read only memory 失效
    电可擦除可编程只读存储器中的保护地址范围

    公开(公告)号：US6009495A

    公开(公告)日：1999-12-28

    申请号：US554667

    申请日：1995-11-08

    申请人： David T. DeRoo ,  Mark D. Nicol ,  David J. DeLisle ,  Saifuddin Fakhruddin ,  Lloyd W. Gauthier ,  Robert A. Kohtz

    发明人： David T. DeRoo ,  Mark D. Nicol ,  David J. DeLisle ,  Saifuddin Fakhruddin ,  Lloyd W. Gauthier ,  Robert A. Kohtz

    IPC分类号： G06F9/30 ,  G06F9/32 ,  G06F9/445 ,  G06F9/50 ,  G06F12/14 ,  G06F21/00 ,  G06F12/00

    CPC分类号： G06F9/5016 ,  G06F12/1433 ,  G06F21/79 ,  G06F9/30101 ,  G06F9/32 ,  G06F9/4401 ,  G06F12/1441

    摘要： An interface between the host CPU and the programmably memory, providing an address, data and read/write control signals to create a non-volatile sector within the programmable memory. In an embodiment when the system reset is de-asserted immediately after power-on, the size of the protected EEPROM area is sensed on special strapping option pins and automatically configures the non-volatile sector. This allows the size of the protected area to be changed on the manufacturing line as needed for different applications. Once configured to protect a specific size and location in the non-volatile memory, the invention prevents the write control signal to the memory to be asserted when the address of the data access requested by the CPU is in the protected area of the memory. This has the effect of preventing modification of the protected area by a sector modification algorithm.

    摘要翻译： 主机CPU和可编程存储器之间的接口，提供地址，数据和读/写控制信号，以在可编程存储器内创建非易失性扇区。 在系统复位在上电之后立即被断开的实施例中，受保护的EEPROM区域的大小在特殊的捆扎选项引脚上被感测并自动配置非易失性扇区。 这样就可以根据不同的应用需要在生产线上改变保护区的大小。 一旦配置为保护非易失性存储器中的特定尺寸和位置，本发明防止当CPU请求的数据访问的地址处于存储器的保护区域时，对存储器的写入控制信号被断言。 这具有通过扇区修改算法防止保护区域的修改的效果。

    Hardware based interface for emulation of a standard system control processor
    8.
    发明授权
    Hardware based interface for emulation of a standard system control processor 失效
    用于仿真标准系统控制处理器的硬件接口

    公开(公告)号：US5696987A

    公开(公告)日：1997-12-09

    申请号：US622924

    申请日：1996-03-27

    申请人： David J. DeLisle ,  Saifuddin Fakhruddin ,  Lloyd Gauthier ,  Robert A. Kohtz

    发明人： David J. DeLisle ,  Saifuddin Fakhruddin ,  Lloyd Gauthier ,  Robert A. Kohtz

    IPC分类号： G06F9/30 ,  G06F9/32 ,  G06F9/445 ,  G06F9/50 ,  G06F11/26 ,  G06F12/06 ,  G06F21/00 ,  G06F9/00

    CPC分类号： G06F9/32 ,  G06F11/261 ,  G06F12/0623 ,  G06F21/79 ,  G06F9/30101 ,  G06F9/30141 ,  G06F9/4401 ,  G06F9/5016

    摘要： A relatively fast system control processor, such as an Intel 8051, is substituted for an Intel 8042 microprocessor in a PC/AT type compatible personal computer. In one embodiment of the invention, a System Control Processor Interface (SCPI) is provided between the central processing unit (CPU) and the system control processor (SCP) to maintain compatibility with the PC/AT bus. The combination of the faster SCP and the SCPI interface improves the overall system performance. Control circuitry is also provided for setting the A20 signal relatively quickly to allow memory access above one megabyte. In an alternate embodiment of the invention, a Mouse Keyboard Interface (MKI) is provided. The MKI provides even quicker switching of the Gate A20 signal by eliminating the need to interrupt the SCP. The MKI also provides support for a type PS/2 mouse.

    摘要翻译： 相对较快的系统控制处理器（如Intel 8051）代替了PC / AT型兼容个人计算机中的Intel 8042微处理器。 在本发明的一个实施例中，在中央处理单元（CPU）和系统控制处理器（SCP）之间提供系统控制处理器接口（SCPI），以保持与PC / AT总线的兼容性。 更快的SCP和SCPI接口的组合提高了整体系统性能。 还提供控制电路用于相对快速地设置A20信号，以允许高于1兆字节的存储器访问。 在本发明的替代实施例中，提供了一种鼠标键盘接口（MKI）。 通过消除对中断SCP的需要，MKI可以更快地切换Gate A20信号。 MKI还提供对PS / 2型鼠标的支持。

    Hardware based interface for mode switching to access memory above one megabyte
    9.
    再颁专利
    Hardware based interface for mode switching to access memory above one megabyte 失效
    基于硬件的接口，用于模式切换，访问存储器高于1兆字节

    公开(公告)号：USRE35480E

    公开(公告)日：1997-03-18

    申请号：US317757

    申请日：1994-10-04

    申请人： David J. DeLisle ,  Saifuddin Fakhruddin ,  Lloyd Gauthier ,  Robert A. Kohtz

    发明人： David J. DeLisle ,  Saifuddin Fakhruddin ,  Lloyd Gauthier ,  Robert A. Kohtz

    IPC分类号： G06F9/30 ,  G06F9/32 ,  G06F9/445 ,  G06F9/50 ,  G06F11/26 ,  G06F12/06 ,  G06F21/00 ,  G06F12/00

    CPC分类号： G06F9/32 ,  G06F11/261 ,  G06F12/0623 ,  G06F21/79 ,  G06F9/30101 ,  G06F9/30141 ,  G06F9/4401 ,  G06F9/5016

    摘要： A relatively fast system control processor, such as an Intel 8051, is substituted for an Intel 8042 microprocessor in a PC/AT type compatible personal computer. In one embodiment of the invention, a System Control Processor Interface (SCPI) is provided between the central processing unit (CPU) and the system control processor (SCP) to maintain compatibility with the PC/AT bus. The combination of the faster SCP and the SCPI interface improves the overall system performance. Control circuitry is also provided for setting the A20 signal relatively quickly to allow memory access above one megabyte. In an alternate embodiment of the invention, a Mouse Keyboard Interface (MKI) is provided. The MKI provides even quicker switching of the Gate A20 signal by eliminating the need to interrupt the SCP. The MKI also provides support for a type PS/2 mouse.

    摘要翻译： 相对较快的系统控制处理器（如Intel 8051）代替了PC / AT型兼容个人计算机中的Intel 8042微处理器。 在本发明的一个实施例中，在中央处理单元（CPU）和系统控制处理器（SCP）之间提供系统控制处理器接口（SCPI），以保持与PC / AT总线的兼容性。 更快的SCP和SCPI接口的组合提高了整体系统性能。 还提供控制电路用于相对快速地设置A20信号，以允许高于1兆字节的存储器访问。 在本发明的替代实施例中，提供了一种鼠标键盘接口（MKI）。 通过消除对中断SCP的需要，MKI可以更快地切换Gate A20信号。 MKI还提供对PS / 2型鼠标的支持。

    Control system and method for multiple rate disk drive data transfer with a single oscillator
    10.
    发明授权
    Control system and method for multiple rate disk drive data transfer with a single oscillator 失效
    使用单个振荡器进行多速率磁盘驱动器数据传输的控制系统和方法

    公开(公告)号：US5291588A

    公开(公告)日：1994-03-01

    申请号：US455818

    申请日：1989-12-18

    申请人： Robert A. Kohtz ,  Mark D. Nicol

    发明人： Robert A. Kohtz ,  Mark D. Nicol

    IPC分类号： G06F3/06 ,  G11B20/10 ,  G06F3/00

    CPC分类号： G06F3/0601 ,  G11B20/10 ,  G06F2003/0692

    摘要： A computer disk drive control adapts the rate of data transfer between a disk drive and a CPU to correspond to one of three industry standard transfer rates. The timing of disk controller signals is provided for by a two phase state machine that receives a signal representative of a selected data transfer rate and generates disk controller signals of the appropriate frequency and configuration. Such disk controller signals cause a disk controller to effect data transfer at the selected rate. In a preferred embodiment, the two phase state machine is driven by two opposite phases of a single 24 MHz clock.

    摘要翻译： 计算机磁盘驱动器控制可以适应磁盘驱动器和CPU之间的数据传输速率，以符合三种工业标准传输速率之一。 磁盘控制器信号的定时由两相状态机提供，该相位状态机接收代表所选数据传输速率的信号，并产生适当频率和配置的磁盘控制器信号。 这样的磁盘控制器信号使磁盘控制器以选定的速率进行数据传输。 在优选实施例中，两相状态机由单个24MHz时钟的两个相反相驱动。