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1.发明授权Determining whether thread fetch operation will be blocked due to processing of another thread 有权确定线程提取操作是否由于处理另一个线程而被阻塞公开(公告)号：US07010669B2
公开(公告)日：2006-03-07
申请号：US10682427
申请日：2003-10-10
IPC分类号： G06F9/50
CPC分类号： G06F9/4881 , G06F9/3851
摘要： In a multi-threaded processor, thread priority variables are set up in memory. According to an embodiment of the present invention, several conditions are monitored so as to determine an indication of instruction side starvation may be approaching. If such starvation is approaching, the starvation is resolved upon the expiration of a threshold counter or the like.
摘要翻译： 在多线程处理器中，线程优先级变量被设置在内存中。 根据本发明的实施例，监视几个条件，以便确定指令侧饥饿的指示可能正在接近。 如果这样的饥饿正在临近，饥饿在阈值计数器等到期后解决。
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2.发明授权公开(公告)号：US06651158B2
公开(公告)日：2003-11-18
申请号：US09888274
申请日：2001-06-22
IPC分类号： G06F946
CPC分类号： G06F9/4881 , G06F9/3851
摘要： In a multi-threaded processor, thread priority variables are set up in memory. According to an embodiment of the present invention, several conditions are monitored so as to determine an indication of instruction side starvation may be approaching. If such starvation is approaching, the starvation is resolved upon the expiration of a threshold counter or the like.
摘要翻译： 在多线程处理器中，线程优先级变量被设置在内存中。 根据本发明的实施例，监视几个条件，以便确定指令侧饥饿的指示可能正在接近。 如果这样的饥饿正在临近，饥饿在阈值计数器等到期后解决。
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3.发明授权Method and apparatus for assigning thread priority in a processor or the like 有权用于在处理器等中分配线程优先级的方法和装置公开(公告)号：US08850165B2
公开(公告)日：2014-09-30
申请号：US13155055
申请日：2011-06-07
CPC分类号： G06F9/4881 , G06F9/3851
摘要： In a multi-threaded processor, thread priority variables are set up in memory. The actual assignment of thread priority is based on the expiration of a thread precedence counter. To further augment, the effectiveness of the thread precedence counters, starting counters are associated with each thread that serve as a multiplier for the value to be used in the thread precedence counter. The value in the starting counters are manipulated so as to prevent one thread from getting undue priority to the resources of the multi-threaded processor.
摘要翻译： 在多线程处理器中，线程优先级变量被设置在内存中。 线程优先级的实际分配基于线程优先级计数器的到期。 为了进一步扩展，线程优先级计数器的有效性，起始计数器与用作在线程优先级计数器中使用的值的乘数的每个线程相关联。 操作起始计数器中的值以防止一个线程对多线程处理器的资源不适当地优先。
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4.发明申请Method and Apparatus for Assigning Thread Priority in a Processor or the Like 有权用于在处理器等中分配线程优先级的方法和装置公开(公告)号：US20110239221A1
公开(公告)日：2011-09-29
申请号：US13155055
申请日：2011-06-07
IPC分类号： G06F9/46
CPC分类号： G06F9/4881 , G06F9/3851
摘要： In a multi-threaded processor, thread priority variables are set up in memory. The actual assignment of thread priority is based on the expiration of a thread precedence counter. To further augment, the effectiveness of the thread precedence counters, starting counters are associated with each thread that serve as a multiplier for the value to be used in the thread precedence counter. The value in the starting counters are manipulated so as to prevent one thread from getting undue priority to the resources of the multi-threaded processor.
摘要翻译： 在多线程处理器中，线程优先级变量被设置在内存中。 线程优先级的实际分配基于线程优先级计数器的到期。 为了进一步扩展，线程优先级计数器的有效性，起始计数器与用作在线程优先级计数器中使用的值的乘数的每个线程相关联。 操作起始计数器中的值以防止一个线程对多线程处理器的资源不适当地优先。
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公开(公告)号：US07877583B2
公开(公告)日：2011-01-25
申请号：US12267394
申请日：2008-11-07
IPC分类号： G06F9/30
CPC分类号： G06F9/4881 , G06F9/3851
摘要： In a multi-threaded processor, thread priority variables are set up in memory. The actual assignment of thread priority is based on the expiration of a thread precedence counter. To further augment, the effectiveness of the thread precedence counters, starting counters are associated with each thread that serve as a multiplier for the value to be used in the thread precedence counter. The value in the starting counters are manipulated so as to prevent one thread from getting undue priority to the resources of the multi-threaded processor.
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6.发明授权Method and apparatus for assigning thread priority in a processor or the like 有权在处理器等中分配线程优先级的方法和装置公开(公告)号：US07454600B2
公开(公告)日：2008-11-18
申请号：US09888273
申请日：2001-06-22
IPC分类号： G06F9/46
CPC分类号： G06F9/4881 , G06F9/3851
摘要： In a multi-threaded processor, thread priority variables are set up in memory. The actual assignment of thread priority is based on the expiration of a thread precedence counter. To further augment, the effectiveness of the thread precedence counters, starting counters are associated with each thread that serve as a multiplier for the value to be used in the thread precedence counter. The value in the starting counters are manipulated so as to prevent one thread from getting undue priority to the resources of the multi-threaded processor.
摘要翻译： 在多线程处理器中，线程优先级变量被设置在内存中。 线程优先级的实际分配基于线程优先级计数器的到期。 为了进一步扩展，线程优先级计数器的有效性，起始计数器与用作在线程优先级计数器中使用的值的乘数的每个线程相关联。 操作起始计数器中的值以防止一个线程对多线程处理器的资源不适当地优先。
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7.发明授权Method and apparatus for assigning thread priority in a processor or the like 有权在处理器等中分配线程优先级的方法和装置公开(公告)号：US07987346B2
公开(公告)日：2011-07-26
申请号：US13011711
申请日：2011-01-21
IPC分类号： G06F9/30
CPC分类号： G06F9/4881 , G06F9/3851
摘要： In a multi-threaded processor, thread priority variables are set up in memory. The actual assignment of thread priority is based on the expiration of a thread precedence counter. To further augment, the effectiveness of the thread precedence counters, starting counters are associated with each thread that serve as a multiplier for the value to be used in the thread precedence counter. The value in the starting counters are manipulated so as to prevent one thread from getting undue priority to the resources of the multi-threaded processor.
摘要翻译： 在多线程处理器中，线程优先级变量被设置在内存中。 线程优先级的实际分配基于线程优先级计数器的到期。 为了进一步扩展，线程优先级计数器的有效性，起始计数器与用作在线程优先级计数器中使用的值的乘数的每个线程相关联。 操作起始计数器中的值以防止一个线程对多线程处理器的资源不适当地优先。
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公开(公告)号：US06467027B1
公开(公告)日：2002-10-15
申请号：US09475746
申请日：1999-12-30
申请人： Alan B. Kyker , Darrell D. Boggs
发明人： Alan B. Kyker , Darrell D. Boggs
IPC分类号： G06F1200
CPC分类号： G06F9/3812 , G06F12/0875
摘要： A method for maintaining an instruction in a pipelined processor using inuse fields. The method involves receiving a read request for an instruction, sending the instruction in response to the read request and setting an inuse field associated with the instruction to inuse. Alternate embodiments of the method involve transmitting the instruction in response to the read request, receiving a notification of instruction retirement and resetting the inuse field in the ITLB. The method can also be used in the ICACHE in which inuse fields are associated with each instruction stored in the ICACHE. Other embodiments of the method can be used concurrently in the ITLB and the ICACHE as a resource tracking mechanism to maintain resources.
摘要翻译： 一种用于使用使用字段来维护在流水线处理器中的指令的方法。 该方法包括接收对指令的读取请求，响应于读取请求发送指令并设置与该指令相关联的使用字段以使用。 该方法的替代实施例涉及响应于读请求发送指令，接收指令退出通知并重置ITLB中的使用字段。 该方法也可以用在ICACHE中，其中使用字段与存储在ICACHE中的每个指令相关联。 该方法的其他实施例可以在ITLB和ICACHE中同时使用作为资源跟踪机制来维护资源。
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公开(公告)号：US06591344B2
公开(公告)日：2003-07-08
申请号：US10218628
申请日：2002-08-15
申请人： Alan B. Kyker , Darrell D. Boggs
发明人： Alan B. Kyker , Darrell D. Boggs
IPC分类号： G06F1200
CPC分类号： G06F9/3812 , G06F12/0875
摘要： A method for maintaining an instruction in a pipelined processor using inuse fields. The method involves receiving a read request for an instruction, sending the instruction in response to the read request and setting an inuse field associated with the instruction to inuse. Alternate embodiments of the method involve transmitting the instruction in response to the read request, receiving a notification of instruction retirement and resetting the inuse field in the ITLB. The method can also be used in the ICACHE in which inuse fields are associated with each instruction stored in the ICACHE. Other embodiments of the method can be used concurrently in the ITLB and the ICACHE as a resource tracking mechanism to maintain resources.
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10.发明授权Branch recovery mechanism to reduce processor front end stall time by providing path information for both correct and incorrect instructions mixed in the instruction pool 失效分支恢复机制通过为指令池中混合的正确和不正确指令提供路径信息来减少处理器前端失速时间
公开(公告)号：US6026477A
公开(公告)日：2000-02-15
申请号：US2000
申请日：1997-12-31
申请人： Alan B. Kyker , Darrell D. Boggs
发明人： Alan B. Kyker , Darrell D. Boggs
IPC分类号： G06F9/38
CPC分类号： G06F9/3861 , G06F9/3836 , G06F9/3855 , G06F9/3857
摘要： An improved branch recovery mechanism includes an instruction fetch unit, an instruction decode stage, a branch prediction unit coupled to the decode stage for predicting whether the branch instruction will be taken, and an instruction pool for receiving and storing micro-ops. After a mispredicted branch is detected, micro-ops corresponding to a correct path are loaded into the instruction pool without waiting for the mispredicted branch instruction to be retired. By immediately loading the correct path into the instruction pool, Front End stall time can be reduced. Micro-ops in the instruction pool are distinguished based on path information for each micro-op stored in the instruction pool. The micro-ops corresponding to the mispredicted path are deleted as quickly as possible without committing their execution results to architectural state.
摘要翻译： 改进的分支恢复机制包括指令提取单元，指令解码级，耦合到解码级的分支预测单元，用于预测是否采用分支指令;以及指令池，用于接收和存储微操作。 在检测到错误预测的分支之后，对应于正确路径的微操作被加载到指令池中，而不等待错误预测的分支指令被退出。 通过立即将正确的路径加载到指令池中，可以减少前端失速时间。 基于存储在指令池中的每个微操作的路径信息区分指令池中的微操作。 与错误预测路径相对应的微操作被尽可能快地删除，而不会将其执行结果提交到架构状态。
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