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1.发明授权Method and apparatus for assigning thread priority in a processor or the like 有权在处理器等中分配线程优先级的方法和装置公开(公告)号：US07987346B2
公开(公告)日：2011-07-26
申请号：US13011711
申请日：2011-01-21
IPC分类号： G06F9/30
CPC分类号： G06F9/4881 , G06F9/3851
摘要： In a multi-threaded processor, thread priority variables are set up in memory. The actual assignment of thread priority is based on the expiration of a thread precedence counter. To further augment, the effectiveness of the thread precedence counters, starting counters are associated with each thread that serve as a multiplier for the value to be used in the thread precedence counter. The value in the starting counters are manipulated so as to prevent one thread from getting undue priority to the resources of the multi-threaded processor.
摘要翻译： 在多线程处理器中，线程优先级变量被设置在内存中。 线程优先级的实际分配基于线程优先级计数器的到期。 为了进一步扩展，线程优先级计数器的有效性，起始计数器与用作在线程优先级计数器中使用的值的乘数的每个线程相关联。 操作起始计数器中的值以防止一个线程对多线程处理器的资源不适当地优先。
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2.发明授权Method and apparatus for assigning thread priority in a processor or the like 有权用于在处理器等中分配线程优先级的方法和装置公开(公告)号：US08850165B2
公开(公告)日：2014-09-30
申请号：US13155055
申请日：2011-06-07
CPC分类号： G06F9/4881 , G06F9/3851
摘要： In a multi-threaded processor, thread priority variables are set up in memory. The actual assignment of thread priority is based on the expiration of a thread precedence counter. To further augment, the effectiveness of the thread precedence counters, starting counters are associated with each thread that serve as a multiplier for the value to be used in the thread precedence counter. The value in the starting counters are manipulated so as to prevent one thread from getting undue priority to the resources of the multi-threaded processor.
摘要翻译： 在多线程处理器中，线程优先级变量被设置在内存中。 线程优先级的实际分配基于线程优先级计数器的到期。 为了进一步扩展，线程优先级计数器的有效性，起始计数器与用作在线程优先级计数器中使用的值的乘数的每个线程相关联。 操作起始计数器中的值以防止一个线程对多线程处理器的资源不适当地优先。
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3.发明申请Method and Apparatus for Assigning Thread Priority in a Processor or the Like 有权用于在处理器等中分配线程优先级的方法和装置公开(公告)号：US20110239221A1
公开(公告)日：2011-09-29
申请号：US13155055
申请日：2011-06-07
IPC分类号： G06F9/46
CPC分类号： G06F9/4881 , G06F9/3851
摘要： In a multi-threaded processor, thread priority variables are set up in memory. The actual assignment of thread priority is based on the expiration of a thread precedence counter. To further augment, the effectiveness of the thread precedence counters, starting counters are associated with each thread that serve as a multiplier for the value to be used in the thread precedence counter. The value in the starting counters are manipulated so as to prevent one thread from getting undue priority to the resources of the multi-threaded processor.
摘要翻译： 在多线程处理器中，线程优先级变量被设置在内存中。 线程优先级的实际分配基于线程优先级计数器的到期。 为了进一步扩展，线程优先级计数器的有效性，起始计数器与用作在线程优先级计数器中使用的值的乘数的每个线程相关联。 操作起始计数器中的值以防止一个线程对多线程处理器的资源不适当地优先。
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公开(公告)号：US07877583B2
公开(公告)日：2011-01-25
申请号：US12267394
申请日：2008-11-07
IPC分类号： G06F9/30
CPC分类号： G06F9/4881 , G06F9/3851
摘要： In a multi-threaded processor, thread priority variables are set up in memory. The actual assignment of thread priority is based on the expiration of a thread precedence counter. To further augment, the effectiveness of the thread precedence counters, starting counters are associated with each thread that serve as a multiplier for the value to be used in the thread precedence counter. The value in the starting counters are manipulated so as to prevent one thread from getting undue priority to the resources of the multi-threaded processor.
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5.发明授权Method and apparatus for assigning thread priority in a processor or the like 有权在处理器等中分配线程优先级的方法和装置公开(公告)号：US07454600B2
公开(公告)日：2008-11-18
申请号：US09888273
申请日：2001-06-22
IPC分类号： G06F9/46
CPC分类号： G06F9/4881 , G06F9/3851
摘要： In a multi-threaded processor, thread priority variables are set up in memory. The actual assignment of thread priority is based on the expiration of a thread precedence counter. To further augment, the effectiveness of the thread precedence counters, starting counters are associated with each thread that serve as a multiplier for the value to be used in the thread precedence counter. The value in the starting counters are manipulated so as to prevent one thread from getting undue priority to the resources of the multi-threaded processor.
摘要翻译： 在多线程处理器中，线程优先级变量被设置在内存中。 线程优先级的实际分配基于线程优先级计数器的到期。 为了进一步扩展，线程优先级计数器的有效性，起始计数器与用作在线程优先级计数器中使用的值的乘数的每个线程相关联。 操作起始计数器中的值以防止一个线程对多线程处理器的资源不适当地优先。
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6.发明授权
公开(公告)号：US6094717A
公开(公告)日：2000-07-25
申请号：US126658
申请日：1998-07-31
IPC分类号： G06F9/38
CPC分类号： G06F9/3836 , G06F9/3838 , G06F9/3842 , G06F9/3857 , G06F9/3861
摘要： A computer processor includes a multiplexer having a first input, a second input, a third input, and an output. The processor further includes a scheduler coupled to the multiplexer first input, an execution unit coupled to the multiplexer output, and a replay system that has an input coupled to the multiplexer output. The replay system includes a first checker coupled to the replay system input and the second multiplexer input, and a second checker coupled to the first checker and the third multiplexer input.
摘要翻译： 计算机处理器包括具有第一输入，第二输入，第三输入和输出的多路复用器。 处理器还包括耦合到多路复用器第一输入的调度器，耦合到多路复用器输出的执行单元和具有耦合到多路复用器输出的输入的重播系统。 重播系统包括耦合到重放系统输入和第二多路复用器输入的第一检查器，以及耦合到第一检验器和第三多路复用器输入的第二检验器。
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7.发明授权Determining whether thread fetch operation will be blocked due to processing of another thread 有权确定线程提取操作是否由于处理另一个线程而被阻塞公开(公告)号：US07010669B2
公开(公告)日：2006-03-07
申请号：US10682427
申请日：2003-10-10
IPC分类号： G06F9/50
CPC分类号： G06F9/4881 , G06F9/3851
摘要： In a multi-threaded processor, thread priority variables are set up in memory. According to an embodiment of the present invention, several conditions are monitored so as to determine an indication of instruction side starvation may be approaching. If such starvation is approaching, the starvation is resolved upon the expiration of a threshold counter or the like.
摘要翻译： 在多线程处理器中，线程优先级变量被设置在内存中。 根据本发明的实施例，监视几个条件，以便确定指令侧饥饿的指示可能正在接近。 如果这样的饥饿正在临近，饥饿在阈值计数器等到期后解决。
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8.发明授权公开(公告)号：US06651158B2
公开(公告)日：2003-11-18
申请号：US09888274
申请日：2001-06-22
IPC分类号： G06F946
CPC分类号： G06F9/4881 , G06F9/3851
摘要： In a multi-threaded processor, thread priority variables are set up in memory. According to an embodiment of the present invention, several conditions are monitored so as to determine an indication of instruction side starvation may be approaching. If such starvation is approaching, the starvation is resolved upon the expiration of a threshold counter or the like.
摘要翻译： 在多线程处理器中，线程优先级变量被设置在内存中。 根据本发明的实施例，监视几个条件，以便确定指令侧饥饿的指示可能正在接近。 如果这样的饥饿正在临近，饥饿在阈值计数器等到期后解决。
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公开(公告)号：US06170038A
公开(公告)日：2001-01-02
申请号：US09447078
申请日：1999-11-22
IPC分类号： G06F926
CPC分类号： G06F12/0875
摘要： A cache memory is constituted with a data array and control logic. The data array includes a number of data lines, and the control logic operates to store a number of trace segments of instructions in the data lines, including trace segments that span multiple data lines. In one embodiment, each trace segment includes one or more trace segment members having one or more instructions, with each trace segment member occupying one data line, and the data lines of a multi-line trace segment being sequentially associated (logically). Retrieval of the trace segment members of a multi-line trace segment is accomplished by first locating the data line storing the first trace segment member of the trace segment, and then successively locating the remaining data lines storing the remaining trace segment members based on the data lines' logical sequential associations.
摘要翻译： 高速缓冲存储器由数据阵列和控制逻辑构成。 数据阵列包括许多数据线，并且控制逻辑操作以在数据线中存储多条迹线段，包括跨越多个数据线的迹线段。 在一个实施例中，每个跟踪段包括具有一个或多个指令的一个或多个跟踪段成员，每个跟踪段成员占据一个数据线，并且多行跟踪段的数据线被顺序地相关联（逻辑地）。 通过首先定位存储跟踪段的第一跟踪段成员的数据线，然后基于数据连续定位存储剩余跟踪段成员的剩余数据线，来检索多行跟踪段的跟踪段成员 行的逻辑顺序关联。
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公开(公告)号：USRE44494E1
公开(公告)日：2013-09-10
申请号：US10996328
申请日：2004-11-24
CPC分类号： G06F1/02 , G06F1/06 , G06F1/08 , G06F9/30145 , G06F9/383 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3869 , G06F15/7832
摘要： A processor including a first execution core section clocked to perform execution operations at a first clock frequency, and a second execution core section clocked to perform execution operations at a second clock frequency which is different than the first clock frequency. The second execution core section runs faster and includes a data cache and critical ALU functions, while the first execution core section includes latency-tolerant functions such as instruction fetch and decode units and non-critical ALU functions. The processor may further include an I/O ring which may be still slower than the first execution core section. Optionally, the first execution core section may include a third execution core section whose clock rate is between that of the first and second execution core sections. Clock multipliers/dividers may be used between the various sections to derive their clocks from a single source, such as the I/O clock.
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