Serial Peripheral Interface for a Transceiver Integrated Circuit
    1.
    发明申请
    Serial Peripheral Interface for a Transceiver Integrated Circuit 审中-公开
    收发器集成电路的串行外设接口

    公开(公告)号:US20090138638A1

    公开(公告)日:2009-05-28

    申请号:US12163880

    申请日:2008-06-27

    IPC分类号: G06F13/42 G06F13/40

    摘要: A protocol may be implemented in a smart transceiver device that contains the physical (PHY) and media access control (MAC) layers of a protocol stack. In various embodiments, a serial peripheral interface (SPI) based design may be used. A protocol is disclosed that may be used to provide control and data transfer to and from the smart transceiver device. In particular, an exemplary format for the protocol, the commands, and responses is disclosed. In a further embodiment, a method for mode synchronization that does not require the use of additional pins and can be accomplished with the standard SPI pins is disclosed. In another embodiment, a method that permits frame timing on the SPI bus to be restored without resetting the slave device is disclosed.

    摘要翻译: 可以在包含协议栈的物理(PHY)和媒体访问控制(MAC)层的智能收发器设备中实现协议。 在各种实施例中,可以使用基于串行外设接口(SPI)的设计。 公开了可用于向智能收发器设备提供控制和数据传输的协议。 具体地,公开了用于协议,命令和响应的示例性格式。 在另一个实施例中,公开了一种不需要使用附加引脚并可通过标准SPI引脚实现的模式同步的方法。 在另一个实施例中,公开了允许在SPI总线上进行帧定时而不重置从设备的方法。

    Base element for a multiplexer structure and corresponding multiplexer structure
    2.
    发明授权
    Base element for a multiplexer structure and corresponding multiplexer structure 失效
    用于多路复用器结构的基本元件和相应的多路复用器结构

    公开(公告)号:US06972600B2

    公开(公告)日:2005-12-06

    申请号:US10344549

    申请日:2001-08-22

    申请人: Thomas Glos

    发明人: Thomas Glos

    IPC分类号: G06F13/40 H04J3/04 H03K19/20

    CPC分类号: H04J3/047 G06F13/4068

    摘要: A divided multiplexer structure which can be used to replace a tristate bus, comprising node elements which are embodied in such a way that no feedback can occur in between the interconnected nodes. For this purpose, each node includes at least one feedback-free connection port.

    摘要翻译: 一种分割的多路复用器结构,其可以用于替换三态总线,包括节点元件,其以这样的方式实现,使得在互连节点之间不会发生反馈。 为此,每个节点至少包括一个无反馈的连接端口。