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公开(公告)号：US20120170699A1
公开(公告)日：2012-07-05
申请号：US12982854
申请日：2010-12-30
申请人： Dennis M. Fischette , Rohit Kumar
发明人： Dennis M. Fischette , Rohit Kumar
IPC分类号： H03D3/24
CPC分类号： H03D3/24 , H03L7/1075 , H03L2207/06
摘要： A method and mechanism for reducing lock time of a dual-path phase lock loop (PLL). The PLL comprises a dual-path low-pass filter (LPF). The LPF includes a first filter and a second filter. The first filter comprises a passive second-order lead-lag low-pass filter. The second filter comprises a first-order lag low-pass filter. During a lock-acquisition state, an impedance value within the second stage is bypassed, which increases the loop bandwidth of the PLL. In addition, a resistance within the first stage is increased in order to increase the gain of the first stage and maintain stability within the PLL. During a lock state, the impedance value may no longer be bypassed and the increased resistance may be returned to its original value.
摘要翻译： 一种减少双路锁相环（PLL）锁定时间的方法和机制。 PLL包括双通道低通滤波器（LPF）。 LPF包括第一过滤器和第二过滤器。 第一滤波器包括无源二阶超前延迟低通滤波器。 第二滤波器包括一阶滞后低通滤波器。 在锁定获取状态期间，旁路第二级中的阻抗值，这增加了PLL的环路带宽。 此外，增加第一级内的电阻以增加第一级的增益并保持PLL内的稳定性。 在锁定状态期间，阻抗值可能不再被旁路，并且增加的电阻可能返回到其原始值。
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公开(公告)号：US08503597B2
公开(公告)日：2013-08-06
申请号：US12982854
申请日：2010-12-30
申请人： Dennis M. Fischette , Rohit Kumar
发明人： Dennis M. Fischette , Rohit Kumar
IPC分类号： H03D3/24
CPC分类号： H03D3/24 , H03L7/1075 , H03L2207/06
摘要： A method and mechanism for reducing lock time of a dual-path phase lock loop (PLL). The PLL comprises a dual-path low-pass filter (LPF). The LPF includes a first filter and a second filter. The first filter comprises a passive second-order lead-lag low-pass filter. The second filter comprises a first-order lag low-pass filter. During a lock-acquisition state, an impedance value within the second stage is bypassed, which increases the loop bandwidth of the PLL. In addition, a resistance within the first stage is increased in order to increase the gain of the first stage and maintain stability within the PLL. During a lock state, the impedance value may no longer be bypassed and the increased resistance may be returned to its original value.
摘要翻译： 一种减少双路锁相环（PLL）锁定时间的方法和机制。 PLL包括双通道低通滤波器（LPF）。 LPF包括第一过滤器和第二过滤器。 第一滤波器包括无源二阶超前延迟低通滤波器。 第二滤波器包括一阶滞后低通滤波器。 在锁定获取状态期间，旁路第二级中的阻抗值，这增加了PLL的环路带宽。 此外，增加第一级内的电阻以增加第一级的增益并保持PLL内的稳定性。 在锁定状态期间，阻抗值可能不再被旁路，并且增加的电阻可能返回到其原始值。
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公开(公告)号：US08570113B2
公开(公告)日：2013-10-29
申请号：US12821534
申请日：2010-06-23
申请人： Dennis M. Fischette
发明人： Dennis M. Fischette
CPC分类号： H03L7/0995 , H03L7/093 , H03L7/1075
摘要： A method and circuitry for calibrating the gain of a VCO (voltage controlled oscillator) is disclosed. In one embodiment, a circuit includes a comparator configured to provide a first indication if the VCO gain is not within the specified gain range, and a second indication if the VCO is within the specified gain range. The circuit further includes a control unit configured to, upon occurrence of at least a first cycle of a clock signal, cause adjustment of the VCO gain responsive to receiving the first indication. For each one or more successive cycles of the clock signal, the control unit is configured to cause corresponding adjustments of the VCO gain until the comparator provides the second indication. The control unit is configured to discontinue adjustments to the VCO gain responsive to receiving the second indication.
摘要翻译： 公开了一种用于校准VCO（压控振荡器）的增益的方法和电路。 在一个实施例中，电路包括比较器，其被配置为：如果VCO增益不在规定的增益范围内，则提供第一指示，以及如果VCO在规定的增益范围内，则提供第二指示。 该电路还包括控制单元，该控制单元被配置为在发生时钟信号的至少第一周期时，响应于接收到第一指示而引起VCO增益的调整。 对于时钟信号的每个一个或多个连续周期，控制单元被配置为引起VCO增益的相应调整，直到比较器提供第二指示。 控制单元被配置为响应于接收到第二指示而停止对VCO增益的调整。
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公开(公告)号：US20110304407A1
公开(公告)日：2011-12-15
申请号：US12813071
申请日：2010-06-10
IPC分类号： H03L5/00
摘要： A circuit and method for calibrating a VCO (voltage controlled oscillator) is disclosed. In one embodiment, a circuit includes a VCO and a bias control circuit coupled to a tail node of the VCO. An amplitude control unit may also be coupled to the tail node, wherein the amplitude control unit is configured to determine the amplitude of a VCO output signal based on a voltage present on the tail node. The amplitude control unit may also be configured to generate a bias voltage based on the amplitude of the VCO output signal and a target voltage. The bias control circuit may be coupled to receive the bias voltage from the amplitude control unit and may be further configured to adjust the voltage on the tail node based on the received bias voltage.
摘要翻译： 公开了一种用于校准VCO（压控振荡器）的电路和方法。 在一个实施例中，电路包括耦合到VCO的尾部节点的VCO和偏置控制电路。 幅度控制单元还可以耦合到尾部节点，其中，幅度控制单元被配置为基于存在于尾部节点上的电压来确定VCO输出信号的幅度。 幅度控制单元还可以被配置为基于VCO输出信号的幅度和目标电压来产生偏置电压。 偏置控制电路可以被耦合以从幅度控制单元接收偏置电压，并且还可以被配置为基于所接收的偏置电压来调整尾部节点上的电压。
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公开(公告)号：US08134417B2
公开(公告)日：2012-03-13
申请号：US12813071
申请日：2010-06-10
摘要： A circuit and method for calibrating a VCO (voltage controlled oscillator) is disclosed. In one embodiment, a circuit includes a VCO and a bias control circuit coupled to a tail node of the VCO. An amplitude control unit may also be coupled to the tail node, wherein the amplitude control unit is configured to determine the amplitude of a VCO output signal based on a voltage present on the tail node. The amplitude control unit may also be configured to generate a bias voltage based on the amplitude of the VCO output signal and a target voltage. The bias control circuit may be coupled to receive the bias voltage from the amplitude control unit and may be further configured to adjust the voltage on the tail node based on the received bias voltage.
摘要翻译： 公开了一种用于校准VCO（压控振荡器）的电路和方法。 在一个实施例中，电路包括耦合到VCO的尾部节点的VCO和偏置控制电路。 幅度控制单元还可以耦合到尾部节点，其中，幅度控制单元被配置为基于存在于尾部节点上的电压来确定VCO输出信号的幅度。 幅度控制单元还可以被配置为基于VCO输出信号的幅度和目标电压来产生偏置电压。 偏置控制电路可以被耦合以从幅度控制单元接收偏置电压，并且还可以被配置为基于所接收的偏置电压来调整尾部节点上的电压。
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公开(公告)号：US20110316639A1
公开(公告)日：2011-12-29
申请号：US12821534
申请日：2010-06-23
申请人： Dennis M. Fischette
发明人： Dennis M. Fischette
CPC分类号： H03L7/0995 , H03L7/093 , H03L7/1075
摘要： A method and circuitry for calibrating the gain of a VCO (voltage controlled oscillator) is disclosed. In one embodiment, a circuit includes a comparator configured to provide a first indication if the VCO gain is not within the specified gain range, and a second indication if the VCO is within the specified gain range. The circuit further includes a control unit configured to, upon occurrence of at least a first cycle of a clock signal, cause adjustment of the VCO gain responsive to receiving the first indication. For each one or more successive cycles of the clock signal, the control unit is configured to cause corresponding adjustments of the VCO gain until the comparator provides the second indication. The control unit is configured to discontinue adjustments to the VCO gain responsive to receiving the second indication.
摘要翻译： 公开了一种用于校准VCO（压控振荡器）的增益的方法和电路。 在一个实施例中，电路包括比较器，其被配置为：如果VCO增益不在规定的增益范围内，则提供第一指示，以及如果VCO在规定的增益范围内，则提供第二指示。 该电路还包括控制单元，该控制单元被配置为在发生时钟信号的至少第一周期时，响应于接收到第一指示而引起VCO增益的调整。 对于时钟信号的每个一个或多个连续周期，控制单元被配置为引起VCO增益的相应调整，直到比较器提供第二指示。 控制单元被配置为响应于接收到第二指示而停止对VCO增益的调整。
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