公开(公告)号：US20070018690A1

公开(公告)日：2007-01-25

申请号：US11186608

申请日：2005-07-21

申请人： Derick Behrends ,  Ryan Kivimagi ,  Chihhung Liao

发明人： Derick Behrends ,  Ryan Kivimagi ,  Chihhung Liao

IPC分类号： H03K19/096

CPC分类号： H03K19/0963

摘要： An apparatus and method provide logically controlled masking of one or more maskable data bits from a plurality of data bits that are input to a dynamic logic circuit. No masking logic and attendant delay penalty is coupled in the data path that is not needed for unmasked bits from the plurality of data bits that do not need masking. A system clock has a precharge phase and an evaluate phase. A first clock buffer is coupled to a precharge switch and precharges a dynamic node during the precharge phase. A second clock buffer having substantially the same delay from system clock input to an output of the second clock buffer is gated by a derivative of a mask. The output of the second clock buffer controls one or more switches in series with switches controlled by the maskable data bits.

摘要翻译： 一种装置和方法从输入到动态逻辑电路的多个数据位提供一个或多个可屏蔽数据位的逻辑控制掩蔽。 在不需要掩蔽的多个数据位中的未屏蔽位不需要的数据路径中耦合掩蔽逻辑和伴随的延迟损耗。 系统时钟具有预充电阶段和评估阶段。 第一时钟缓冲器耦合到预充电开关并且在预充电阶段期间预充电动态节点。 具有从系统时钟输入到第二时钟缓冲器的输出的基本相同延迟的第二时钟缓冲器由掩模的导数来选通。 第二时钟缓冲器的输出控制与由可屏蔽数据位控制的开关串联的一个或多个开关。

公开(公告)号：US08780604B2

公开(公告)日：2014-07-15

申请号：US13535802

申请日：2012-06-28

申请人： Chihhung Liao ,  Phu Nguyen ,  Vimal R. Patel ,  George F. Paulik ,  Peder J. Paulson ,  Brian J. Reed ,  Salvatore N. Storino

发明人： Chihhung Liao ,  Phu Nguyen ,  Vimal R. Patel ,  George F. Paulik ,  Peder J. Paulson ,  Brian J. Reed ,  Salvatore N. Storino

IPC分类号： G11C17/12

CPC分类号： G06F17/5027 ,  G11C7/18 ,  G11C17/16 ,  G11C29/027 ,  G11C2029/4402

摘要： An eFuse circuit may include a wordline, a first eFuse, a first logic gate, a first blowFET, and a first bitline discharge device. The first eFuse may have a first end coupled to the wordline and a second end. The first eFuse may have a first resistance when unblown and a second resistance when blown. The first logic gate may be coupled to the first end of the first eFuse. The first logic gate may be capable of driving enough current to blow the first eFuse. The first blowFET may have a source coupled to a first supply voltage, a gate coupled to a program signal, and a drain coupled to the second end of the first eFuse. The first bitline discharge device may have a gate coupled to the second end of the first eFuse, a source coupled to the first supply voltage, and a drain coupled to a first bitline.

摘要翻译： eFuse电路可以包括字线，第一eFuse，第一逻辑门，第一blowFET和第一位线放电装置。 第一eFuse可以具有耦合到字线的第一端和第二端。 第一个eFuse可以在未吹塑时具有第一个阻力，当吹制时可能具有第二个阻力。 第一逻辑门可以耦合到第一eFuse的第一端。 第一逻辑门可能能够驱动足够的电流来吹动第一eFuse。 第一blowFET可以具有耦合到第一电源电压的源极，耦合到编程信号的栅极和耦合到第一eFuse的第二端的漏极。 第一位线放电装置可以具有耦合到第一eFuse的第二端的栅极，耦合到第一电源电压的源极和耦合到第一位线的漏极。

公开(公告)号：US07215154B2

公开(公告)日：2007-05-08

申请号：US11186608

申请日：2005-07-21

申请人： Derick Gardner Behrends ,  Ryan Charles Kivimagi ,  Chihhung Liao

发明人： Derick Gardner Behrends ,  Ryan Charles Kivimagi ,  Chihhung Liao

IPC分类号： H03K19/096

CPC分类号： H03K19/0963

摘要： An apparatus and method provide logically controlled masking of one or more maskable data bits from a plurality of data bits that are input to a dynamic logic circuit. No masking logic and attendant delay penalty is coupled in the data path that is not needed for unmasked bits from the plurality of data bits that do not need masking. A system clock has a precharge phase and an evaluate phase. A first clock buffer is coupled to a precharge switch and precharges a dynamic node during the precharge phase. A second clock buffer having substantially the same delay from system clock input to an output of the second clock buffer is gated by a derivative of a mask. The output of the second clock buffer controls one or more switches in series with switches controlled by the maskable data bits.

公开(公告)号：US20140003120A1

公开(公告)日：2014-01-02

申请号：US13535802

申请日：2012-06-28

申请人： Chihhung Liao ,  Phu Nguyen ,  Vimal R. Patel ,  George F. Paulik ,  Peder J. Paulson ,  Brian J. Reed ,  Salvatore N. Storino

发明人： Chihhung Liao ,  Phu Nguyen ,  Vimal R. Patel ,  George F. Paulik ,  Peder J. Paulson ,  Brian J. Reed ,  Salvatore N. Storino

IPC分类号： G11C17/16 ,  G06F17/50

CPC分类号： G06F17/5027 ,  G11C7/18 ,  G11C17/16 ,  G11C29/027 ,  G11C2029/4402

摘要： An eFuse circuit may include a wordline, a first eFuse, a first logic gate, a first blowFET, and a first bitline discharge device. The first eFuse may have a first end coupled to the wordline and a second end. The first eFuse may have a first resistance when unblown and a second resistance when blown. The first logic gate may be coupled to the first end of the first eFuse. The first logic gate may be capable of driving enough current to blow the first eFuse. The first blowFET may have a source coupled to a first supply voltage, a gate coupled to a program signal, and a drain coupled to the second end of the first eFuse. The first bitline discharge device may have a gate coupled to the second end of the first eFuse, a source coupled to the first supply voltage, and a drain coupled to a first bitline.

摘要翻译： eFuse电路可以包括字线，第一eFuse，第一逻辑门，第一blowFET和第一位线放电装置。 第一eFuse可以具有耦合到字线的第一端和第二端。 第一个eFuse可以在未吹塑时具有第一个阻力，当吹制时可能具有第二个阻力。 第一逻辑门可以耦合到第一eFuse的第一端。 第一逻辑门可能能够驱动足够的电流来吹动第一eFuse。 第一blowFET可以具有耦合到第一电源电压的源极，耦合到编程信号的栅极和耦合到第一eFuse的第二端的漏极。 第一位线放电装置可以具有耦合到第一eFuse的第二端的栅极，耦合到第一电源电压的源极和耦合到第一位线的漏极。