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9 条记录 (耗时 0.011 秒)

    Maskable dynamic logic
    1.
    发明授权
    Maskable dynamic logic 失效

    公开(公告)号：US07215154B2

    公开(公告)日：2007-05-08

    申请号：US11186608

    申请日：2005-07-21

    申请人： Derick Gardner Behrends ,  Ryan Charles Kivimagi ,  Chihhung Liao

    发明人： Derick Gardner Behrends ,  Ryan Charles Kivimagi ,  Chihhung Liao

    IPC分类号： H03K19/096

    CPC分类号： H03K19/0963

    摘要： An apparatus and method provide logically controlled masking of one or more maskable data bits from a plurality of data bits that are input to a dynamic logic circuit. No masking logic and attendant delay penalty is coupled in the data path that is not needed for unmasked bits from the plurality of data bits that do not need masking. A system clock has a precharge phase and an evaluate phase. A first clock buffer is coupled to a precharge switch and precharges a dynamic node during the precharge phase. A second clock buffer having substantially the same delay from system clock input to an output of the second clock buffer is gated by a derivative of a mask. The output of the second clock buffer controls one or more switches in series with switches controlled by the maskable data bits.

    Flood mode implementation for continuous bitline local evaluation circuit
    2.
    发明授权
    Flood mode implementation for continuous bitline local evaluation circuit 失效
    连续位线局部评估电路的洪水模式实现

    公开(公告)号：US07133320B2

    公开(公告)日：2006-11-07

    申请号：US10981153

    申请日：2004-11-04

    申请人： Chad Allen Adams ,  Derick Gardner Behrends ,  Ryan Charles Kivimagi

    发明人： Chad Allen Adams ,  Derick Gardner Behrends ,  Ryan Charles Kivimagi

    IPC分类号： G11C7/00

    CPC分类号： G11C29/50 ,  G11C11/41

    摘要： A method, an apparatus, and a computer program product are provided for flood mode implementation of SRAM cells that employ a continuous bitline local evaluation circuit. Flood mode testing is used to weed out marginal SRAM cells by stressing the SRAM cells. Flood mode is induced by beginning with a normal write operation. After new data values have been forced into the SRAM cells, then the write signal is chopped off. A delay block keeps the wordline signal at the high supply, and the SRAM cells go into flood mode. At this juncture marginal cells can be easily detected and later mapped to redundant cells.

    摘要翻译： 提供了一种方法，装置和计算机程序产品，用于采用连续位线局部评估电路的SRAM单元的泛洪模式实现。 洪水模式测试用于通过强调SRAM单元来清除边缘SRAM单元。 通过开始正常的写操作来引发洪泛模式。 在新的数据值被强制进入SRAM单元之后，写入信号被切断。 延迟块将字线信号保持在高电源，SRAM单元进入泛洪模式。 在这个关键点，边缘细胞可以很容易地被检测，并且稍后映射到冗余细胞。

    Method and Enhanced SRAM Redundancy Circuit for Reducing Wiring and Required Number of Redundant Elements
    4.
    发明申请
    Method and Enhanced SRAM Redundancy Circuit for Reducing Wiring and Required Number of Redundant Elements 审中-公开
    方法和增强型SRAM冗余电路，用于减少接线和所需的冗余元件数量

    公开(公告)号：US20080112219A1

    公开(公告)日：2008-05-15

    申请号：US11868575

    申请日：2007-10-08

    申请人： Derick Gardner Behrends ,  Peter Thomas Freiburger ,  Ryan Charles Kivimagi ,  Daniel Mark Nelson

    发明人： Derick Gardner Behrends ,  Peter Thomas Freiburger ,  Ryan Charles Kivimagi ,  Daniel Mark Nelson

    IPC分类号： G11C11/34

    CPC分类号： G11C29/846

    摘要： A method and enhanced Static Random Access Memory (SRAM) redundancy circuit reduce wiring and the required number of redundant elements, and a design structure on which the subject SRAM redundancy circuit resides is provided. A bitline redundancy mechanism allows the swapping of a pair of bitlines for a redundant pair of bit columns. Two of the adjacent bitlines are swapped out at a time, one even and one odd. The swap is accomplished by steering the data around the bad columns and adding redundant columns on the end that are steered in when needed.

    摘要翻译： 一种方法和增强的静态随机存取存储器（SRAM）冗余电路减少了布线和所需数量的冗余元件，并且提供了存在被摄体SRAM冗余电路的设计结构。 位线冗余机制允许对一对位列进行交换。 两个相邻的位线一次被换出，一个偶数和一个奇数。 交换是通过围绕不良列操作数据进行转换，并在需要时引导的末尾添加冗余列。

    Method for reducing wiring and required number of redundant elements
    8.
    发明授权
    Method for reducing wiring and required number of redundant elements 失效
    减少布线和所需数量的冗余元件的方法

    公开(公告)号：US07443744B2

    公开(公告)日：2008-10-28

    申请号：US11559431

    申请日：2006-11-14

    申请人： Derick Gardner Behrends ,  Peter Thomas Freiburger ,  Ryan Charles Kivimagi ,  Daniel Mark Nelson

    发明人： Derick Gardner Behrends ,  Peter Thomas Freiburger ,  Ryan Charles Kivimagi ,  Daniel Mark Nelson

    IPC分类号： G11C7/00

    CPC分类号： G11C29/846

    摘要： A method and enhanced Static Random Access Memory (SRAM) redundancy circuit reduce wiring and the required number of redundant elements. A bitline redundancy mechanism allows the swapping of a pair of bitlines for a redundant pair of bit columns. Two of the adjacent bitlines are swapped out at a time, one even and one odd. The swap is accomplished by steering the data around the bad columns and adding redundant columns on the end that are steered in when needed.

    摘要翻译： 一种方法和增强的静态随机存取存储器（SRAM）冗余电路减少了布线和所需数量的冗余元件。 位线冗余机制允许对一对位列进行交换。 两个相邻的位线一次被换出，一个偶数和一个奇数。 交换是通过围绕不良列操作数据进行转换，并在需要时引导的末尾添加冗余列。

    Flood mode implementation for continuous bitline local evaluation circuit
    9.
    发明授权
    Flood mode implementation for continuous bitline local evaluation circuit 失效
    连续位线局部评估电路的洪水模式实现

    公开(公告)号：US07283411B2

    公开(公告)日：2007-10-16

    申请号：US11552791

    申请日：2006-10-25

    申请人： Chad Allen Adams ,  Derick Gardner Behrends ,  Ryan Charles Kivimagi

    发明人： Chad Allen Adams ,  Derick Gardner Behrends ,  Ryan Charles Kivimagi

    IPC分类号： G11C7/00

    CPC分类号： G11C29/50 ,  G11C11/41

    摘要： A method, an apparatus, and a computer program product are provided for flood mode implementation of SRAM cells that employ a continuous bitline local evaluation circuit. Flood mode testing is used to weed out marginal SRAM cells by stressing the SRAM cells. Flood mode is induced by beginning with a normal write operation. After new data values have been forced into the SRAM cells, then the write signal is chopped off. A delay block keeps the wordline signal at the high supply, and the SRAM cells go into flood mode. At this juncture marginal cells can be easily detected and later mapped to redundant cells.

    摘要翻译： 提供了一种方法，装置和计算机程序产品，用于采用连续位线局部评估电路的SRAM单元的泛洪模式实现。 洪水模式测试用于通过强调SRAM单元来清除边缘SRAM单元。 通过开始正常的写操作来引发洪泛模式。 在新的数据值被强制进入SRAM单元之后，写入信号被切断。 延迟块将字线信号保持在高电源，SRAM单元进入泛洪模式。 在这个关键点，边缘细胞可以很容易地被检测，并且稍后映射到冗余细胞。