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    LAYOUT TO MINIMIZE FET VARIATION IN SMALL DIMENSION PHOTOLITHOGRAPHY
    2.
    发明申请
    LAYOUT TO MINIMIZE FET VARIATION IN SMALL DIMENSION PHOTOLITHOGRAPHY 有权
    布局以最小化小尺寸光刻机中的FET变化

    公开(公告)号：US20130175631A1

    公开(公告)日：2013-07-11

    申请号：US13345439

    申请日：2012-01-06

    申请人： Derick G. Behrends ,  Todd A. Christensen ,  Travis R. Hebig ,  Michael Launsbach ,  Daniel M. Nelson

    发明人： Derick G. Behrends ,  Todd A. Christensen ,  Travis R. Hebig ,  Michael Launsbach ,  Daniel M. Nelson

    IPC分类号： H01L27/11 ,  H01L21/28 ,  G06F17/50

    CPC分类号： H01L27/1104 ,  G11C5/025 ,  H01L21/28123 ,  H01L27/0207

    摘要： A semiconductor chip has shapes on a particular level that are small enough to require a first mask and a second mask, the first mask and the second mask used in separate exposures during processing. A circuit on the semiconductor chip requires close tracking between a first and a second FET (field effect transistor). For example, the particular level may be a gate shape level. Separate exposures of gate shapes using the first mask and the second mask will result in poorer FET tracking (e.g., gate length, threshold voltage) than for FETs having gate shapes defined by only the first mask. FET tracking is selectively improved by laying out a circuit such that selective FETs are defined by the first mask. In particular, static random access memory (SRAM) design benefits from close tracking of six or more FETs in an SRAM cell.

    摘要翻译： 半导体芯片具有在足够小以至要求第一掩模和第二掩模的特定等级上的形状，第一掩模和第二掩模在处理期间分开曝光中使用。 半导体芯片上的电路需要在第一和第二FET（场效应晶体管）之间的紧密跟踪。 例如，特定级别可以是门形状级别。 使用第一掩模和第二掩模的栅极形状的单独曝光将导致比仅由第一掩模限定的栅极形状的FET更差的FET跟踪（例如，栅极长度，阈值电压）。 通过布置电路来选择性地提高FET跟踪，使得选择性FET由第一掩模限定。 特别地，静态随机存取存储器（SRAM）设计受益于在SRAM单元中紧密跟踪六个或更多个FET。

    Implementing RC and coupling delay correction for SRAM
    3.
    发明授权
    Implementing RC and coupling delay correction for SRAM 有权
    实现SRAM的RC和耦合延迟校正

    公开(公告)号：US08675427B2

    公开(公告)日：2014-03-18

    申请号：US13414133

    申请日：2012-03-07

    申请人： Derick G. Behrends ,  Todd A. Christensen ,  Travis R. Hebig ,  Michael Launsbach ,  Daniel M. Nelson

    发明人： Derick G. Behrends ,  Todd A. Christensen ,  Travis R. Hebig ,  Michael Launsbach ,  Daniel M. Nelson

    IPC分类号： G11C7/00

    CPC分类号： G11C7/12 ,  G11C11/419

    摘要： A method and circuit for implementing delay correction in static random access memory (SRAM), and a design structure on which the subject circuit resides are provided. The SRAM circuit includes a precharge enable signal coupled between precharge near and precharge far signals and wordline near and wordline far signals of the SRAM. A precharge pull down device is coupled between the precharge far signal and ground and is controlled responsive to the precharge enable signal to decrease a time delay of the falling transition of the precharge far signal. A respective word line pull up device is coupled between a respective wordline far signal and a voltage supply rail and is controlled responsive to the precharge enable signal to increase wordline voltage level upon a rising transition of the wordline far signal.

    摘要翻译： 一种用于实现静态随机存取存储器（SRAM）中的延迟校正的方法和电路，以及设置有被摄体电路所在的设计结构。 SRAM电路包括预充电接近和预充电远信号以及SRAM的字线附近和字线远信号之间的预充电使能信号。 预充电下拉装置耦合在预充电远信号和地之间，并且响应于预充电使能信号被控制，以减小预充电远信号的下降转换的时间延迟。 相应的字线上拉器件耦合在相应的字线远信号和电压供应轨之间，并且响应于预充电使能信号被控制，以在字线远信号的上升转变时增加字线电压电平。

    IMPLEMENTING RC AND COUPLING DELAY CORRECTION FOR SRAM
    6.
    发明申请
    IMPLEMENTING RC AND COUPLING DELAY CORRECTION FOR SRAM 有权
    实现SRAM的RC和耦合延迟校正

    公开(公告)号：US20130235681A1

    公开(公告)日：2013-09-12

    申请号：US13414133

    申请日：2012-03-07

    申请人： Derick G. Behrends ,  Todd A. Christensen ,  Travis R. Hebig ,  Michael Launsbach ,  Daniel M. Nelson

    发明人： Derick G. Behrends ,  Todd A. Christensen ,  Travis R. Hebig ,  Michael Launsbach ,  Daniel M. Nelson

    IPC分类号： G11C7/12 ,  G06F17/50

    CPC分类号： G11C7/12 ,  G11C11/419

    摘要： A method and circuit for implementing delay correction in static random access memory (SRAM), and a design structure on which the subject circuit resides are provided. The SRAM circuit includes a precharge enable signal coupled between precharge near and precharge far signals and wordline near and wordline far signals of the SRAM. A precharge pull down device is coupled between the precharge far signal and ground and is controlled responsive to the precharge enable signal to decrease a time delay of the falling transition of the precharge far signal. A respective word line pull up device is coupled between a respective wordline far signal and a voltage supply rail and is controlled responsive to the precharge enable signal to increase wordline voltage level upon a rising transition of the wordline far signal.

    摘要翻译： 一种用于实现静态随机存取存储器（SRAM）中的延迟校正的方法和电路，以及设置有被摄体电路所在的设计结构。 SRAM电路包括预充电接近和预充电远信号以及SRAM的字线附近和字线远信号之间的预充电使能信号。 预充电下拉装置耦合在预充电远信号和地之间，并且响应于预充电使能信号被控制以减小预充电远信号的下降转换的时间延迟。 相应的字线上拉器件耦合在相应的字线远信号和电压供应轨之间，并且响应于预充电使能信号被控制，以在字线远信号的上升转变时增加字线电压电平。

    Implementing mulitple mask lithography timing variation mitigation
    8.
    发明授权
    Implementing mulitple mask lithography timing variation mitigation 失效
    实现多种掩模光刻时序变化缓解

    公开(公告)号：US08578304B1

    公开(公告)日：2013-11-05

    申请号：US13558468

    申请日：2012-07-26

    申请人： Derick G. Behrends ,  Todd A. Christensen ,  Travis R. Hebig ,  Michael Launsbach

    发明人： Derick G. Behrends ,  Todd A. Christensen ,  Travis R. Hebig ,  Michael Launsbach

    IPC分类号： G06F17/50

    CPC分类号： G03F1/70

    摘要： A method, system and computer program product are provided for implementing multiple mask lithography timing variation mitigation for a multiple mask polysilicon (PC) process. An application specific integrated circuit (ASIC) library includes at least one circuit device for a first mask, and at least one circuit device for a second mask. Critical hold time paths and critical setup time paths are identified in a circuit design. For critical hold time paths, circuit devices in the critical hold time paths are placed on a single mask of either the first mask or the second mask. For critical setup time paths, path delays are reduced by providing a mixture of circuit devices on the first mask and the second mask.

    摘要翻译： 提供了一种方法，系统和计算机程序产品，用于实现多掩模多晶硅（PC）处理的多掩模光刻定时变化减轻。 专用集成电路（ASIC）库包括用于第一掩模的至少一个电路装置和用于第二掩模的至少一个电路装置。 在电路设计中标识临界保持时间路径和关键建立时间路径。 对于临界保持时间路径，临界保持时间路径中的电路设备放置在第一掩模或第二掩模的单个掩模上。 对于关键的建立时间路径，通过在第一掩模和第二掩模上提供电路装置的混合来减少路径延迟。

    IMPLEMENTING POWER SAVING SELF POWERING DOWN LATCH STRUCTURE
    9.
    发明申请
    IMPLEMENTING POWER SAVING SELF POWERING DOWN LATCH STRUCTURE 有权
    实现节能自卸机构结构

    公开(公告)号：US20130222031A1

    公开(公告)日：2013-08-29

    申请号：US13404096

    申请日：2012-02-24

    申请人： Derick G. Behrends ,  Todd A. Christensen ,  Travis R. Hebig ,  Michael Launsbach

    发明人： Derick G. Behrends ,  Todd A. Christensen ,  Travis R. Hebig ,  Michael Launsbach

    IPC分类号： H03K3/289

    CPC分类号： H03K3/012 ,  H03K3/0375

    摘要： A method and circuits for implementing power saving self powering down latch operation, and a design structure on which the subject circuit resides are provided. A master slave latch includes a virtual power supply connection. At least one connection control device is coupled between the virtual power supply connection and a voltage supply rail. A driver gate applies a power down signal driving the at least one connection control device to control the at least one connection control device during a self power down mode. The driver gate combines a self power down input signal and a latch data output signal to generate the power down signal.

    摘要翻译： 一种用于实现省电自掉电锁存器操作的方法和电路，以及设置有该电路所在的设计结构。 主从锁存器包括虚拟电源连接。 至少一个连接控制装置耦合在虚拟电源连接和电压供应导轨之间。 驱动器门施加驱动所述至少一个连接控制装置的掉电信号，以在自省电模式期间控制所述至少一个连接控制装置。 驱动器门组合自省电输入信号和锁存数据输出信号以产生掉电信号。

    Implementing power saving self powering down latch structure
    10.
    发明授权
    Implementing power saving self powering down latch structure 有权
    实现节能自卸锁结构

    公开(公告)号：US08669800B2

    公开(公告)日：2014-03-11

    申请号：US13404096

    申请日：2012-02-24

    申请人： Derick G. Behrends ,  Todd A. Christensen ,  Travis R. Hebig ,  Michael Launsbach

    发明人： Derick G. Behrends ,  Todd A. Christensen ,  Travis R. Hebig ,  Michael Launsbach

    IPC分类号： H03K3/289

    CPC分类号： H03K3/012 ,  H03K3/0375

    摘要： A method and circuits for implementing power saving self powering down latch operation, and a design structure on which the subject circuit resides are provided. A master slave latch includes a virtual power supply connection. At least one connection control device is coupled between the virtual power supply connection and a voltage supply rail. A driver gate applies a power down signal driving the at least one connection control device to control the at least one connection control device during a self power down mode. The driver gate combines a self power down input signal and a latch data output signal to generate the power down signal.

    摘要翻译： 一种用于实现省电自掉电锁存器操作的方法和电路，以及设置有该电路所在的设计结构。 主从锁存器包括虚拟电源连接。 至少一个连接控制装置耦合在虚拟电源连接和电压供应导轨之间。 驱动器门施加驱动所述至少一个连接控制装置的掉电信号，以在自省电模式期间控制所述至少一个连接控制装置。 驱动器门组合自省电输入信号和锁存数据输出信号以产生掉电信号。