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    LAYOUT TO MINIMIZE FET VARIATION IN SMALL DIMENSION PHOTOLITHOGRAPHY
    2.
    发明申请
    LAYOUT TO MINIMIZE FET VARIATION IN SMALL DIMENSION PHOTOLITHOGRAPHY 有权
    布局以最小化小尺寸光刻机中的FET变化

    公开(公告)号：US20130175631A1

    公开(公告)日：2013-07-11

    申请号：US13345439

    申请日：2012-01-06

    申请人： Derick G. Behrends ,  Todd A. Christensen ,  Travis R. Hebig ,  Michael Launsbach ,  Daniel M. Nelson

    发明人： Derick G. Behrends ,  Todd A. Christensen ,  Travis R. Hebig ,  Michael Launsbach ,  Daniel M. Nelson

    IPC分类号： H01L27/11 ,  H01L21/28 ,  G06F17/50

    CPC分类号： H01L27/1104 ,  G11C5/025 ,  H01L21/28123 ,  H01L27/0207

    摘要： A semiconductor chip has shapes on a particular level that are small enough to require a first mask and a second mask, the first mask and the second mask used in separate exposures during processing. A circuit on the semiconductor chip requires close tracking between a first and a second FET (field effect transistor). For example, the particular level may be a gate shape level. Separate exposures of gate shapes using the first mask and the second mask will result in poorer FET tracking (e.g., gate length, threshold voltage) than for FETs having gate shapes defined by only the first mask. FET tracking is selectively improved by laying out a circuit such that selective FETs are defined by the first mask. In particular, static random access memory (SRAM) design benefits from close tracking of six or more FETs in an SRAM cell.

    摘要翻译： 半导体芯片具有在足够小以至要求第一掩模和第二掩模的特定等级上的形状，第一掩模和第二掩模在处理期间分开曝光中使用。 半导体芯片上的电路需要在第一和第二FET（场效应晶体管）之间的紧密跟踪。 例如，特定级别可以是门形状级别。 使用第一掩模和第二掩模的栅极形状的单独曝光将导致比仅由第一掩模限定的栅极形状的FET更差的FET跟踪（例如，栅极长度，阈值电压）。 通过布置电路来选择性地提高FET跟踪，使得选择性FET由第一掩模限定。 特别地，静态随机存取存储器（SRAM）设计受益于在SRAM单元中紧密跟踪六个或更多个FET。

    Implementing RC and coupling delay correction for SRAM
    3.
    发明授权
    Implementing RC and coupling delay correction for SRAM 有权
    实现SRAM的RC和耦合延迟校正

    公开(公告)号：US08675427B2

    公开(公告)日：2014-03-18

    申请号：US13414133

    申请日：2012-03-07

    申请人： Derick G. Behrends ,  Todd A. Christensen ,  Travis R. Hebig ,  Michael Launsbach ,  Daniel M. Nelson

    发明人： Derick G. Behrends ,  Todd A. Christensen ,  Travis R. Hebig ,  Michael Launsbach ,  Daniel M. Nelson

    IPC分类号： G11C7/00

    CPC分类号： G11C7/12 ,  G11C11/419

    摘要： A method and circuit for implementing delay correction in static random access memory (SRAM), and a design structure on which the subject circuit resides are provided. The SRAM circuit includes a precharge enable signal coupled between precharge near and precharge far signals and wordline near and wordline far signals of the SRAM. A precharge pull down device is coupled between the precharge far signal and ground and is controlled responsive to the precharge enable signal to decrease a time delay of the falling transition of the precharge far signal. A respective word line pull up device is coupled between a respective wordline far signal and a voltage supply rail and is controlled responsive to the precharge enable signal to increase wordline voltage level upon a rising transition of the wordline far signal.

    摘要翻译： 一种用于实现静态随机存取存储器（SRAM）中的延迟校正的方法和电路，以及设置有被摄体电路所在的设计结构。 SRAM电路包括预充电接近和预充电远信号以及SRAM的字线附近和字线远信号之间的预充电使能信号。 预充电下拉装置耦合在预充电远信号和地之间，并且响应于预充电使能信号被控制，以减小预充电远信号的下降转换的时间延迟。 相应的字线上拉器件耦合在相应的字线远信号和电压供应轨之间，并且响应于预充电使能信号被控制，以在字线远信号的上升转变时增加字线电压电平。

    IMPLEMENTING RC AND COUPLING DELAY CORRECTION FOR SRAM
    6.
    发明申请
    IMPLEMENTING RC AND COUPLING DELAY CORRECTION FOR SRAM 有权
    实现SRAM的RC和耦合延迟校正

    公开(公告)号：US20130235681A1

    公开(公告)日：2013-09-12

    申请号：US13414133

    申请日：2012-03-07

    申请人： Derick G. Behrends ,  Todd A. Christensen ,  Travis R. Hebig ,  Michael Launsbach ,  Daniel M. Nelson

    发明人： Derick G. Behrends ,  Todd A. Christensen ,  Travis R. Hebig ,  Michael Launsbach ,  Daniel M. Nelson

    IPC分类号： G11C7/12 ,  G06F17/50

    CPC分类号： G11C7/12 ,  G11C11/419

    摘要： A method and circuit for implementing delay correction in static random access memory (SRAM), and a design structure on which the subject circuit resides are provided. The SRAM circuit includes a precharge enable signal coupled between precharge near and precharge far signals and wordline near and wordline far signals of the SRAM. A precharge pull down device is coupled between the precharge far signal and ground and is controlled responsive to the precharge enable signal to decrease a time delay of the falling transition of the precharge far signal. A respective word line pull up device is coupled between a respective wordline far signal and a voltage supply rail and is controlled responsive to the precharge enable signal to increase wordline voltage level upon a rising transition of the wordline far signal.

    摘要翻译： 一种用于实现静态随机存取存储器（SRAM）中的延迟校正的方法和电路，以及设置有被摄体电路所在的设计结构。 SRAM电路包括预充电接近和预充电远信号以及SRAM的字线附近和字线远信号之间的预充电使能信号。 预充电下拉装置耦合在预充电远信号和地之间，并且响应于预充电使能信号被控制以减小预充电远信号的下降转换的时间延迟。 相应的字线上拉器件耦合在相应的字线远信号和电压供应轨之间，并且响应于预充电使能信号被控制，以在字线远信号的上升转变时增加字线电压电平。

    Method and apparatus to limit circuit delay dependence on voltage for single phase transition
    8.
    发明授权
    Method and apparatus to limit circuit delay dependence on voltage for single phase transition 失效
    限制电路延迟依赖于单相电压的方法和装置

    公开(公告)号：US08344782B2

    公开(公告)日：2013-01-01

    申请号：US12613673

    申请日：2009-11-06

    申请人： Derick G. Behrends ,  Todd A. Christensen ,  Travis R. Hebig ,  Daniel M. Nelson

    发明人： Derick G. Behrends ,  Todd A. Christensen ,  Travis R. Hebig ,  Daniel M. Nelson

    IPC分类号： H03H11/26

    CPC分类号： H03K5/1534 ,  H03K5/133

    摘要： A delay circuit receives a data input having an input transition and that generates a data output having an output transition. The delay circuit is powered by a voltage source having a voltage. A first delay element is configured to generate a first data signal with a first edge that has a relatively constant delay relative to the input transition irrespective of the voltage of the voltage source. A second delay element is configured to generate a second data signal with a second edge that has a delay relative to the input transition as a function of the voltage of the voltage source. A selection element causes the output transition at the data output to correspond to a latest selected one of the first edge and the second edge. The delay circuit may be employed in a pulse generating circuit.

    摘要翻译： 延迟电路接收具有输入转变的数据输入并产生具有输出转变的数据输出。 延迟电路由具有电压的电压源供电。 第一延迟元件被配置为产生第一数据信号，其中第一边缘相对于输入转换具有相对恒定的延迟，而与电压源的电压无关。 第二延迟元件被配置为产生具有作为电压源的电压的函数的相对于输入转变的延迟的第二边缘的第二数据信号。 选择元件使得数据输出处的输出转变对应于第一边缘和第二边缘中最新选择的一个。 延迟电路可以用在脉冲发生电路中。

    Method and apparatus to limit circuit delay dependence on voltage
    9.
    发明授权
    Method and apparatus to limit circuit delay dependence on voltage 失效
    限制电路延迟对电压的依赖性的方法和装置

    公开(公告)号：US07714630B2

    公开(公告)日：2010-05-11

    申请号：US12138564

    申请日：2008-06-13

    申请人： Derick G. Behrends ,  Todd A. Christensen ,  Travis R. Hebig ,  Daniel M. Nelson

    发明人： Derick G. Behrends ,  Todd A. Christensen ,  Travis R. Hebig ,  Daniel M. Nelson

    IPC分类号： H03H11/26

    CPC分类号： H03K5/133 ,  H03K2005/00026 ,  H03K2005/0013

    摘要： The present disclosure is an apparatus for generating a decreasing delay with increasing input voltage to a predetermined voltage value at which point the delay may remain constant. The apparatus may include a circuit comprising a voltage regulator receiving an input voltage and two paths of inverters. At least two paths of inverters may be coupled to an input signal, the input signal may be low voltage (e.g. 0) or high voltage (e.g. 1). A first path may be referenced to a reference voltage while the second path may be referenced to the input voltage. The apparatus may include logic gates for receiving the output of each of the first path of inverters and the output of the second path of inverters to generate a desired output. As the input voltage increases, delay of the apparatus may decrease until the input voltage is approximately the same voltage as the reference voltage, at which the delay may remain constant.

    摘要翻译： 本公开是一种用于通过将输入电压增加到预定电压值来产生递减延迟的装置，在该点处延迟可以保持恒定。 该装置可以包括电路，该电路包括接收输入电压的电压调节器和两个逆变器路径。 反相器的至少两个路径可以耦合到输入信号，输入信号可以是低电压（例如0）或高电压（例如1）。 第一路径可以参考参考电压，而第二路径可以参考输入电压。 该装置可以包括逻辑门，用于接收每个逆变器的第一路径的输出和第二路径的反相器的输出以产生期望的输出。 当输入电压增加时，装置的延迟可能减小，直到输入电压与参考电压大致相同的电压，在该电压处延迟可以保持恒定。

    DATA SECURITY FOR DYNAMIC RANDOM ACCESS MEMORY AT POWER-UP
    10.
    发明申请
    DATA SECURITY FOR DYNAMIC RANDOM ACCESS MEMORY AT POWER-UP 失效
    上电时动态随机存取存储器的数据安全

    公开(公告)号：US20120147661A1

    公开(公告)日：2012-06-14

    申请号：US12963965

    申请日：2010-12-09

    申请人： Derick G. Behrends ,  Todd A. Christensen ,  Travis R. Hebig ,  Daniel M. Nelson

    发明人： Derick G. Behrends ,  Todd A. Christensen ,  Travis R. Hebig ,  Daniel M. Nelson

    IPC分类号： G11C11/4072

    CPC分类号： G11C11/4072

    摘要： A circuit and method erase at power-up all data stored in a DRAM chip for increased data security. All the DRAM memory cells are erased by turning on the transistors for the DRAM storage cells simultaneously by driving the wordlines of all the cells to an activated state. With all the devices turned on, the data stored in the memory cells is erased as the voltage of all the cells connected to a common bitline coalesce to a single value. In a preferred embodiment, the wordlines are all turned on simultaneously during a power on reset period. Preferably a power on reset signal is used to drive each logic gate of the pre-decoder portion of the address decoder in order to assert all the wordlines.

    摘要翻译： 电路和方法在上电时擦除存储在DRAM芯片中的所有数据，以提高数据安全性。 通过将所有单元的字线驱动到激活状态，同时通过接通DRAM存储单元的晶体管来擦除所有的DRAM存储单元。 当所有设备都打开时，存储在存储单元中的数据将被擦除，因为连接到通用位线的所有单元的电压合并为单个值。 在优选实施例中，在上电复位周期期间，字线都同时导通。 优选地，上电复位信号用于驱动地址解码器的预解码器部分的每个逻辑门，以便断言所有字线。