利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

18 条记录 (耗时 0.027 秒)

    Systems and methods for memory interface calibration
    8.
    发明授权
    Systems and methods for memory interface calibration 有权
    用于存储器接口校准的系统和方法

    公开(公告)号：US09323538B1

    公开(公告)日：2016-04-26

    申请号：US13539153

    申请日：2012-06-29

    申请人： Ivan Blunno ,  Gordon Raymond Chiu

    发明人： Ivan Blunno ,  Gordon Raymond Chiu

    IPC分类号： G06F3/06 ,  G06F3/01 ,  G06F3/05 ,  G01D18/00 ,  G06F9/44

    CPC分类号： G06F9/44 ,  G11C5/04 ,  G11C29/022 ,  G11C29/028

    摘要： Integrated circuits such as programmable integrated circuits may include calibration circuitry for calibrating memory interface circuitry. The calibration circuitry may include processing circuitry and test circuitry. The processing circuitry may provide instructions to the test circuitry and direct the test circuitry to begin processing at a selected instruction. The test circuitry may retrieve data storage addresses and control signal storage addresses from the instructions. The test circuitry may use the data storage address to retrieve test data from data storage circuitry and may use the control signal storage address to retrieve control signal data from control signal storage circuitry. The control signal, address, and test data may be provided to the memory interface circuitry. The test circuitry may verify data received from the system memory during instruction processing.

    摘要翻译： 诸如可编程集成电路的集成电路可以包括用于校准存储器接口电路的校准电路。 校准电路可以包括处理电路和测试电路。 处理电路可以向测试电路提供指令，并指示测试电路在所选择的指令下开始处理。 测试电路可以从指令中检索数据存储地址和控制信号存储地址。 测试电路可以使用数据存储地址从数据存储电路检索测试数据，并且可以使用控制信号存储地址从控制信号存储电路中检索控制信号数据。 控制信号，地址和测试数据可以被提供给存储器接口电路。 测试电路可以在指令处理期间验证从系统存储器接收到的数据。

    M/A for performing automatic latency optimization on system designs for implementation on programmable hardware
    9.
    发明授权
    M/A for performing automatic latency optimization on system designs for implementation on programmable hardware 有权
    M / A用于对可编程硬件上实现的系统设计执行自动延迟优化

    公开(公告)号：US08918748B1

    公开(公告)日：2014-12-23

    申请号：US13593665

    申请日：2012-08-24

    申请人： Gordon Raymond Chiu ,  Deshanand Singh

    发明人： Gordon Raymond Chiu ,  Deshanand Singh

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5054 ,  G06F2217/84

    摘要： A method for performing latency optimization on a system design to be implemented on a target device includes inserting a variable latency indicator in the system design at a place where latency can be varied. The system design includes pipeline registers at the place where the variable latency indicator is inserted. Latency optimization is then automatically performed on the system design, during a computer aided design flow performed by an electronic Design Automation (EDA) tool, by varying the number of the pipeline registers at the variable latency indicator to obtain optimized latency without affecting system performance of the system design.

    摘要翻译： 用于对要在目标设备上实现的系统设计执行延迟优化的方法包括在等待时间可以变化的地方插入系统设计中的可变等待时间指示符。 系统设计包括插入可变延迟指示器的地方的流水线寄存器。 然后，在由电子设计自动化（EDA）工具执行的计算机辅助设计流程期间，系统设计自动执行延迟优化，方法是通过改变可变延迟指示器上的流水线寄存器的数量来获得优化的延迟，而不会影响系统性能 系统设计。