公开(公告)号：US20070192610A1

公开(公告)日：2007-08-16

申请号：US11351966

申请日：2006-02-10

申请人： Dexter Chun ,  Ajit Patil ,  Cuneyt Fitoz ,  Dwight Gordon ,  Yu-Hsiang Huang ,  Oliver Michaelis

发明人： Dexter Chun ,  Ajit Patil ,  Cuneyt Fitoz ,  Dwight Gordon ,  Yu-Hsiang Huang ,  Oliver Michaelis

IPC分类号： H04L9/00

CPC分类号： G06F21/64 ,  G06F21/575

摘要： Techniques to securely boot up an electronics device (e.g., a cellular phone) from an external storage device are described. Secure data (e.g., a hash digest, a signature, a cryptographic key, and so on) is initially retrieved from a non-writable area of an external memory device (e.g., an one-time programmable (OTP) area of a NAND Flash device). A first program (e.g., a boot program) is retrieved from a writable or main area of the external memory device and authenticated based on the secure data. The first program is enabled for execution if authenticated. A second program may be retrieved from the main area of the external memory device and authenticated based on the secure data. The second program is enabled for execution if authenticated. Additional programs may be retrieved and authenticated. Each program may be authenticated using a secure hash function, a digital signature, and/or some other cryptographic technique.

摘要翻译： 描述了从外部存储设备安全地引导电子设备（例如，蜂窝电话）的技术。 最初从外部存储器件（例如，NAND闪存的一次可编程（OTP））区域的不可写区域检索安全数据（例如，散列摘要，签名，加密密钥等） 设备）。 从外部存储器件的可写或主区域检索第一程序（例如，引导程序），并基于安全数据进行认证。 如果通过验证，第一个程序启用执行。 可以从外部存储设备的主区域检索第二程序，并且基于安全数据进行认证。 如果通过验证，第二个程序启用执行。 可以检索和认证附加程序。 可以使用安全散列函数，数字签名和/或一些其他加密技术来对每个程序进行认证。

公开(公告)号：US20060104115A1

公开(公告)日：2006-05-18

申请号：US10993034

申请日：2004-11-18

申请人： Dexter Chun ,  Ajit Patil ,  Ian Huang ,  Jason Chan ,  Timothy Gold

发明人： Dexter Chun ,  Ajit Patil ,  Ian Huang ,  Jason Chan ,  Timothy Gold

IPC分类号： G11C16/04

CPC分类号： G11C29/028 ,  G06F9/4403 ,  G06F9/44505 ,  G06F11/1068 ,  G11C7/1006 ,  G11C7/1045 ,  G11C7/22 ,  G11C16/04 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/32 ,  G11C29/42 ,  G11C29/50 ,  G11C29/50012 ,  G11C2216/14

摘要： Techniques for quickly and reliably accessing a memory device (e.g., a NAND Flash memory) with adaptive interface timing are described. For memory access with adaptive interface timing, the NAND Flash memory is accessed at an initial memory access rate, which may be the rate predicted to achieve reliable memory access. Error correction coding (ECC), which is often employed for NAND Flash memory, is then used to ensure reliable access of the NAND Flash. For a read operation, one page of data is read at a time from the NAND Flash memory, and the ECC determines whether the page read from the NAND Flash memory contains any errors. If errors are encountered, then a slower memory access rate is selected, and the page with error is read again from the NAND Flash memory at the new rate. The techniques may be used to write data to the NAND Flash memory.

公开(公告)号：US07061804B2

公开(公告)日：2006-06-13

申请号：US10993034

申请日：2004-11-18

申请人： Dexter Tamio Chun ,  Ajit Patil ,  Ian Huang ,  Jason Chan ,  Timothy Gold

发明人： Dexter Tamio Chun ,  Ajit Patil ,  Ian Huang ,  Jason Chan ,  Timothy Gold

IPC分类号： G11C11/34

CPC分类号： G11C29/028 ,  G06F9/4403 ,  G06F9/44505 ,  G06F11/1068 ,  G11C7/1006 ,  G11C7/1045 ,  G11C7/22 ,  G11C16/04 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/32 ,  G11C29/42 ,  G11C29/50 ,  G11C29/50012 ,  G11C2216/14

摘要： Techniques for quickly and reliably accessing a memory device (e.g., a NAND Flash memory) with adaptive interface timing are described. For memory access with adaptive interface timing, the NAND Flash memory is accessed at an initial memory access rate, which may be the rate predicted to achieve reliable memory access. Error correction coding (ECC), which is often employed for NAND Flash memory, is then used to ensure reliable access of the NAND Flash. For a read operation, one page of data is read at a time from the NAND Flash memory, and the ECC determines whether the page read from the NAND Flash memory contains any errors. If errors are encountered, then a slower memory access rate is selected, and the page with error is read again from the NAND Flash memory at the new rate. The techniques may be used to write data to the NAND Flash memory.

摘要翻译： 描述了利用自适应接口定时快速可靠地访问存储器件（例如，NAND闪存）的技术。 对于具有自适应接口定时的存储器访问，NAND闪存以初始存储器访问速率访问，其可以是预测的速率以实现可靠的存储器访问。 然后，通常用于NAND闪存的纠错编码（ECC）用于确保NAND闪存的可靠访问。 对于读取操作，从NAND闪速存储器一次读取一页数据，并且ECC确定从NAND闪速存储器读取的页面是否包含任何错误。 如果遇到错误，则选择较慢的存储器访问速率，并以新的速率从NAND闪存再次读取带有错误的页面。 这些技术可以用于将数据写入NAND闪存。