公开(公告)号：US20150145801A1

公开(公告)日：2015-05-28

申请号：US13619328

申请日：2012-09-14

Applicant: Paolo Angelini ,  Giovanni Carlo Tripoli ,  Ernesto Lasalandra ,  Tommaso Ungaretti ,  Kien Beng Tan ,  Yannick Guedon ,  Dianbo Guo ,  Sze-Kwang Tan

Inventor： Paolo Angelini ,  Giovanni Carlo Tripoli ,  Ernesto Lasalandra ,  Tommaso Ungaretti ,  Kien Beng Tan ,  Yannick Guedon ,  Dianbo Guo ,  Sze-Kwang Tan

IPC: G06F3/044

CPC classification number: G06F3/044 ,  G06F3/0416

Abstract: Capacitance sensing circuits and methods are provided. The capacitance sensing circuit includes a capacitance-to-voltage converter configured to receive a signal from a capacitance to be sensed and to provide an output signal representative of the capacitance, an output chopper configured to convert the output signal of the capacitance-to-voltage converter to a sensed voltage representative of the capacitance to be sensed, an analog accumulator configured to accumulate sensed voltages during an accumulation period of NA sensing cycles and to provide an accumulated analog value, an amplifier configured to amplify the accumulated analog value, and an analog-to-digital converter configured to convert the amplified accumulated analog value to a digital value representative of the capacitance to be sensed. The analog accumulator may include a low pass filter having a frequency response to filter wideband noise.

Abstract translation: 提供电容感测电路和方法。 电容感测电路包括：电容 - 电压转换器，被配置为从要感测的电容接收信号并提供表示电容的输出信号;输出斩波器，被配置为转换电容 - 电压的输出信号 转换器到感测的电压，代表要感测的电容;模拟累加器，被配置为在NA感测周期的累积周期期间累积感测电压并提供累加的模拟值，被配置为放大所累积的模拟值的放大器和模拟 配置为将放大的累积模拟值转换为表示要感测的电容的数字值。 模拟累加器可以包括具有对滤波器宽带噪声的频率响应的低通滤波器。

公开(公告)号：US20110133810A1

公开(公告)日：2011-06-09

申请号：US12633597

申请日：2009-12-08

Applicant: Dianbo Guo ,  Eng Jye Ng ,  Kien Beng Tan

Inventor： Dianbo Guo ,  Eng Jye Ng ,  Kien Beng Tan

IPC: H03L5/00

CPC classification number: H03K17/164

Abstract: In one embodiment, a semiconductor circuit for coupling a first node to a second node includes a first transistor having a first terminal coupled to the first node, a second terminal coupled to the second node, and a control terminal coupled to a control node. The circuit also includes a level shifting circuit having a series diode for coupling a bulk terminal of the first transistor to the control node, and a supply coupling circuit coupled between a first power supply node and the control node.

Abstract translation: 在一个实施例中，用于将第一节点耦合到第二节点的半导体电路包括具有耦合到第一节点的第一终端的第一晶体管，耦合到第二节点的第二终端以及耦合到控制节点的控制终端。 电路还包括具有用于将第一晶体管的体端子耦合到控制节点的串联二极管的电平移动电路和耦合在第一电源节点和控制节点之间的电源耦合电路。

公开(公告)号：US09128573B2

公开(公告)日：2015-09-08

申请号：US13619328

申请日：2012-09-14

Applicant: Paolo Angelini ,  Giovanni Carlo Tripoli ,  Ernesto Lasalandra ,  Tommaso Ungaretti ,  Kien Beng Tan ,  Yannick Guedon ,  Dianbo Guo ,  Sze-Kwang Tan

Inventor： Paolo Angelini ,  Giovanni Carlo Tripoli ,  Ernesto Lasalandra ,  Tommaso Ungaretti ,  Kien Beng Tan ,  Yannick Guedon ,  Dianbo Guo ,  Sze-Kwang Tan

IPC: G06F3/044

CPC classification number: G06F3/044 ,  G06F3/0416

Abstract: Capacitance sensing circuits and methods are provided. The capacitance sensing circuit includes a capacitance-to-voltage converter configured to receive a signal from a capacitance to be sensed and to provide an output signal representative of the capacitance, an output chopper configured to convert the output signal of the capacitance-to-voltage converter to a sensed voltage representative of the capacitance to be sensed, an analog accumulator configured to accumulate sensed voltages during an accumulation period of NA sensing cycles and to provide an accumulated analog value, an amplifier configured to amplify the accumulated analog value, and an analog-to-digital converter configured to convert the amplified accumulated analog value to a digital value representative of the capacitance to be sensed. The analog accumulator may include a low pass filter having a frequency response to filter wideband noise.

Abstract translation: 提供电容感测电路和方法。 电容感测电路包括：电容 - 电压转换器，被配置为从要感测的电容接收信号并提供表示电容的输出信号;输出斩波器，被配置为转换电容 - 电压的输出信号 转换器到感测的电压，代表要感测的电容;模拟累加器，被配置为在NA感测周期的累积周期期间累积感测电压并提供累加的模拟值，被配置为放大所累积的模拟值的放大器和模拟 配置为将放大的累积模拟值转换为表示要感测的电容的数字值。 模拟累加器可以包括具有对滤波器宽带噪声的频率响应的低通滤波器。

公开(公告)号：US08791709B2

公开(公告)日：2014-07-29

申请号：US12972596

申请日：2010-12-20

Applicant: Dianbo Guo

Inventor： Dianbo Guo

IPC: G01R27/26

CPC classification number: B81C99/003 ,  G01R27/2605

Abstract: A micro-electro-mechanical system (MEMS) actuator circuit and method. The circuit includes a current mirror, a voltage divider having an interior contact and coupled between the mirror output and a potential, an operational amplifier having an input coupled to the interior contact and a switch having input/output contacts separately coupled to the amplifier output and the mirror input and having a switch control. The amplifier output can be coupled to a digital control circuit which can be coupled to the switch control contact and to a digital to analog circuit (DAC) which can be coupled to the digital control circuit and to another amplifier input. An enable signal at the switch control couples the switch input/output contacts together. The capacitance of a MEMS capacitor coupled to the mirror output is determined by measurement of time for the amplifier output to switch from one level to another following a change in DAC output potential.

Abstract translation: 微机电系统（MEMS）致动器电路及方法。 该电路包括电流镜，具有内部接触并耦合在反射镜输出和电位之间的分压器，具有耦合到内部触点的输入的运算放大器和具有单独耦合到放大器输出的输入/输出触点的开关，以及 镜像输入并具有开关控制。 放大器输出可以耦合到数字控制电路，数字控制电路可耦合到开关控制触点和耦合到数字控制电路和另一个放大器输入的数模电路（DAC）。 开关控制器处的使能信号将开关输入/输出触点耦合在一起。 耦合到镜像输出的MEMS电容器的电容由DAC输出电位变化后，通过测量放大器输出从一个电平切换到另一个电平的时间来确定。

公开(公告)号：US20110242048A1

公开(公告)日：2011-10-06

申请号：US12972159

申请日：2010-12-17

Applicant: Yannick GUEDON ,  Kien Beng Tan ,  Kusuma Adi Ningrat ,  Dianbo Guo

Inventor： Yannick GUEDON ,  Kien Beng Tan ,  Kusuma Adi Ningrat ,  Dianbo Guo

IPC: G06F3/045

CPC classification number: G06F3/044

Abstract: A capacitive sensing analog front end for a touchscreen system having an improved signal-to-noise ratio includes a capacitance-to-voltage converter having an input for coupling to an external sampling capacitor, a summer having a first input coupled to an output of the capacitance-to-voltage converter, a low pass filter having an input coupled to an output of the summer and an output for providing an output signal; and a sample-and-hold circuit having an input coupled to the output of the low pass filter and an output coupled to a second input of the summer. The signal-to-noise ratio of the touchscreen system is improved by extracting the DC shift of a touch signal during a monitoring period and then subtracting the DC shift before integrating the touch signal.

Abstract translation: 具有改进的信噪比的用于触摸屏系统的电容感测模拟前端包括具有用于耦合到外部采样电容器的输入的电容 - 电压转换器，具有耦合到所述外部采样电容器的输出的第一输入的加法器 电容 - 电压转换器，具有耦合到所述加法器的输出的输入端的低通滤波器和用于提供输出信号的输出; 以及采样保持电路，其具有耦合到所述低通滤波器的输出的输入和耦合到所述夏季的第二输入的输出。 通过在监视期间提取触摸信号的直流偏移，然后在积分触摸信号之前减去直流偏移，来提高触摸屏系统的信噪比。

公开(公告)号：US08004340B2

公开(公告)日：2011-08-23

申请号：US12633597

申请日：2009-12-08

Applicant: Dianbo Guo ,  Eng Jye Ng ,  Kien Beng Tan

Inventor： Dianbo Guo ,  Eng Jye Ng ,  Kien Beng Tan

IPC: H03L5/00

CPC classification number: H03K17/164

Abstract: In one embodiment, a semiconductor circuit for coupling a first node to a second node includes a first transistor having a first terminal coupled to the first node, a second terminal coupled to the second node, and a control terminal coupled to a control node. The circuit also includes a level shifting circuit having a series diode for coupling a bulk terminal of the first transistor to the control node, and a supply coupling circuit coupled between a first power supply node and the control node.

Abstract translation: 在一个实施例中，用于将第一节点耦合到第二节点的半导体电路包括具有耦合到第一节点的第一终端的第一晶体管，耦合到第二节点的第二终端以及耦合到控制节点的控制终端。 电路还包括具有用于将第一晶体管的体端子耦合到控制节点的串联二极管的电平移动电路和耦合在第一电源节点和控制节点之间的电源耦合电路。

公开(公告)号：US20100321100A1

公开(公告)日：2010-12-23

申请号：US12488287

申请日：2009-06-19

Applicant: Dianbo Guo

Inventor： Dianbo Guo

IPC: G05F1/10

CPC classification number: H03K17/6874 ,  H03K17/162 ,  H03K2217/0018

Abstract: A transmission gate includes first and second MOS transistors of opposite conductivity type coupled in parallel with each other. Each transistor includes a body connection that is separately biased by corresponding first and second biasing circuits. The first biasing circuit generates a first bias voltage having a voltage level that is generated as a function of the signal at the first node and a first (for example, positive) reference voltage. The second biasing circuit generates a second bias voltage having a voltage level that is generated as a function of the signal at the first node and a second (for examples ground) reference voltage.

Abstract translation: 传输门包括彼此并联耦合的相反导电类型的第一和第二MOS晶体管。 每个晶体管包括被相应的第一和第二偏置电路单独偏置的主体连接。 第一偏置电路产生具有作为第一节点处的信号和第一（例如，正）参考电压的函数产生的电压电平的第一偏置电压。 第二偏置电路产生具有作为第一节点处的信号和第二（例如，接地）参考电压的函数产生的电压电平的第二偏置电压。

公开(公告)号：US20140092050A1

公开(公告)日：2014-04-03

申请号：US13629877

申请日：2012-09-28

Applicant: Sze-Kwang Tan ,  Yannick Guedon ,  Dianbo Guo

Inventor： Sze-Kwang Tan ,  Yannick Guedon ,  Dianbo Guo

IPC: G06F3/044

CPC classification number: G06F3/044 ,  G06F3/0414 ,  G06F3/0416 ,  G06F2203/04103 ,  G06F2203/04108

Abstract: A readout device for a capacitive sense matrix includes a computer readable storage medium configured to store capacitance data. The capacitance data represents capacitance values of the capacitive sense matrix. The readout device also includes a readout circuit configured to receive a signal from the capacitive sense matrix, the readout circuit being configured based upon the capacitance data. Also described are a readout method and a method of compensating for variations in capacitance.

Abstract translation: 用于电容性感测矩阵的读出装置包括被配置为存储电容数据的计算机可读存储介质。 电容数据表示电容性感测矩阵的电容值。 读出装置还包括被配置为从电容性感测矩阵接收信号的读出电路，读出电路基于电容数据配置。 还描述了补偿电容变化的读出方法和方法。

公开(公告)号：US20120146657A1

公开(公告)日：2012-06-14

申请号：US12965170

申请日：2010-12-10

Applicant: Anthony Junior Casillan ,  Yannick Guedon ,  Dianbo Guo

Inventor： Anthony Junior Casillan ,  Yannick Guedon ,  Dianbo Guo

IPC: G01R31/28

CPC classification number: G06F3/044 ,  G06F3/0416

Abstract: A short circuit detection module for a touch panel includes first and second short circuit detection circuits. The first short circuit detection circuit is coupled to a first conductive line of the touch panel. The first short circuit detection circuit is configured to drive the first conductive line with a first signal having a first logic level. The second short circuit detection circuit is coupled to second, adjacent, conductive line of the touch panel. The second short circuit detection circuit is configured to drive the second conductive line with a second signal having a second logic level that is complementary to the first logic level.

Abstract translation: 用于触摸面板的短路检测模块包括第一和第二短路检测电路。 第一短路检测电路耦合到触摸面板的第一导电线。 第一短路检测电路被配置为用具有第一逻辑电平的第一信号驱动第一导线。 第二短路检测电路耦合到触摸面板的第二相邻的导电线。 第二短路检测电路被配置为用具有与第一逻辑电平互补的第二逻辑电平的第二信号来驱动第二导线。

公开(公告)号：US08054122B2

公开(公告)日：2011-11-08

申请号：US12633777

申请日：2009-12-08

Applicant: Dianbo Guo

Inventor： Dianbo Guo

IPC: H03L5/00

CPC classification number: H03K17/145 ,  H03K2217/0018 ,  H03K2217/0036 ,  H03K2217/0054

Abstract: An analog switch includes a transistor whose source connected to a signal input and whose drain is connected to a signal output. An output of a gate control circuit is connected to the transistor gate. A first input of the gate control circuit is connected to the source of the transistor. The gate control circuit responds to a logic transition of an enable signal received at a second input by pre-charging a substantially constant gate-to-source voltage across the transistor. This voltage is stored by a gate-to-source connected capacitor. In one steady-state logic condition of the enable signal, the gate control circuit operates to turn off the transistor. In another steady-state logic condition of the enable signal, the gate control circuit permits the signal received at the signal input to drive the gate of the transistor with a voltage offset by the substantially constant gate-to-source voltage stored on the capacitor.

Abstract translation: 模拟开关包括其源极连接到信号输入并且其漏极连接到信号输出的晶体管。 栅极控制电路的输出端连接到晶体管栅极。 栅极控制电路的第一输入端连接到晶体管的源极。 栅极控制电路通过对晶体管两端的基本恒定的栅极 - 源极电压进行预充电来响应在第二输入端接收的使能信号的逻辑转换。 该电压由栅极到源极连接的电容器存储。 在使能信号的一个稳态逻辑条件下，栅极控制电路用于关断晶体管。 在使能信号的另一个稳态逻辑条件下，门控制电路允许在信号输入处接收到的信号以由存储在电容器上的基本上恒定的栅极 - 源极电压的电压偏移来驱动晶体管的栅极。