-
公开(公告)号：US07221126B1
公开(公告)日：2007-05-22
申请号：US09561147
申请日：2000-04-28
IPC分类号： H04J3/06
CPC分类号： H04L7/0012 , G06F1/04 , G06F1/12
摘要： A method and apparatus using a clock generator with sequential logic to align the phase of a first clock generated on a receiving integrated circuit (IC) chip to a second clock received by the receiving IC chip. One embodiment of the invention involves a method for aligning the phase of a first clock relative to the phase of a second clock, wherein the first clock is provided by a clock generator in a data processing system. The method includes sampling the second clock with a sampling clock, detecting an edge on the second clock, and stretching the first clock to align the phase of the first clock relative to the phase of the second clock. A second embodiment of the invention involves a data processing system including a transmitting chip, a receiving chip, and a clock generator for aligning the phase of a first clock relative to the phase of a second clock, wherein the second clock is received by the receiving chip. The clock generator includes a sampling circuit to sample the second clock with a sampling clock, a circuit to detect an edge on the second clock, and a sequential logic circuit to stretch the first clock to align the phase of the first clock relative to the phase of the second clock and control the clock generator.
摘要翻译： 一种使用具有顺序逻辑的时钟发生器的方法和装置，用于将在接收集成电路（IC）芯片上产生的第一时钟的相位对准由接收IC芯片接收的第二时钟。 本发明的一个实施例涉及一种用于对准第一时钟相对于第二时钟的相位的方法，其中第一时钟由数据处理系统中的时钟发生器提供。 该方法包括用采样时钟采样第二时钟，检测第二时钟上的边沿，并且拉伸第一时钟以使第一时钟的相位相对于第二时钟的相位对准。 本发明的第二实施例涉及一种包括发射芯片，接收芯片和时钟发生器的数据处理系统，用于对准第一时钟相对于第二时钟的相位的相位，其中第二时钟由接收器接收 芯片。 时钟发生器包括采样电路，用采样时钟对第二时钟进行采样，检测第二时钟的边沿的电路，以及顺序逻辑电路，用于拉伸第一时钟以使第一时钟的相位相对于相位 的第二个时钟并控制时钟发生器。
-
公开(公告)号：US07760530B2
公开(公告)日：2010-07-20
申请号：US11810072
申请日：2007-06-04
IPC分类号： G11C15/00
摘要： Systems, devices, and methods, including executable instructions are provided for resolving content addressable memory (CAM) match address priority. One method includes retaining a first match address as the best match address. Subsequent match addresses are compared to the retained best match address, each match address being associated with a compare cycle during which a selected columnar portion of each CAM entry is compared to a corresponding portion of a search term. The best match address is updated as a result of the comparison.
摘要翻译： 提供系统，设备和方法，包括可执行指令，用于解析内容可寻址存储器（CAM）匹配地址优先级。 一种方法包括保留第一匹配地址作为最佳匹配地址。 将后续匹配地址与保留的最佳匹配地址进行比较，每个匹配地址与比较周期相关联，在该比较周期期间，将每个CAM条目的选定柱状部分与搜索项的相应部分进行比较。 作为比较的结果，最佳匹配地址被更新。
-
公开(公告)号：US20100023804A1
公开(公告)日：2010-01-28
申请号：US12569397
申请日：2009-09-29
IPC分类号： G06F11/20
CPC分类号： G11C29/816 , G11C15/00 , G11C29/44 , G11C29/76
摘要： A method of providing redundancy in a ternary content addressable memory (TCAM), the method including detecting a defective entry in building block in a ternary content addressable memory (TCAM), configuring a failover logic to redirect a software query toward a spare building block and away from the building block with the defective entry, and avoiding in using the building block with the defective entry.
摘要翻译： 一种在三元内容可寻址存储器（TCAM）中提供冗余的方法，所述方法包括检测三元内容可寻址存储器（TCAM）中的构建块中的缺陷条目，配置故障转移逻辑以将软件查询重定向到备用构建块，以及 远离具有缺陷进入的构件块，并且避免使用具有缺陷入口的构造块。
-
公开(公告)号：US07624313B2
公开(公告)日：2009-11-24
申请号：US11092028
申请日：2005-03-28
CPC分类号： G11C29/816 , G11C15/00 , G11C29/44 , G11C29/76
摘要： In an embodiment of the invention, a method of providing redundancy in a ternary content addressable memory (TCAM) includes: detecting a defective entry in a ternary content addressable memory (TCAM); marking the defective entry so that the defective entry is visible to a software; and avoiding in using the defective entry. For data that normally would have been written into the defective entry, the data is written into an entry that is subsequent to the defective entry. In another embodiment, the redundancy is provided in a CAM instead of a TCAM.
摘要翻译： 在本发明的一个实施例中，在三元内容可寻址存储器（TCAM）中提供冗余的方法包括：检测三元内容可寻址存储器（TCAM）中的缺陷条目; 标记有缺陷的条目，使得缺陷条目对于软件是可见的; 并避免使用有缺陷的条目。 对于通常将被写入有缺陷的条目的数据，数据被写入到缺陷输入之后的条目中。 在另一个实施例中，冗余被提供在CAM而不是TCAM中。
-
5.发明授权公开(公告)号：US06490654B2
公开(公告)日：2002-12-03
申请号：US09127491
申请日：1998-07-31
IPC分类号： G06F1212
CPC分类号： G06F12/121 , G06F21/00
摘要： A cache memory replacement algorithm replaces cache lines based on the likelihood that cache lines will not be needed soon. A cache memory in accordance with the present invention includes a plurality of cache lines that are accessed associatively, with a count entry associated with each cache line storing a count value that defines a replacement class. The count entry is typically loaded with a count value when the cache line is accessed, with the count value indicating the likelihood that the contents of cache lines will be needed soon. In other words, data which is likely to be needed soon is assigned a higher replacement class, while data that is more speculative and less likely to be needed soon is assigned a lower replacement class. When the cache memory becomes full, the replacement algorithm selects for replacement those cache lines having the lowest replacement class. Accordingly, the cache lines selected for replacement contain the most speculative data in the cache that is least likely to be needed soon.
摘要翻译： 高速缓存存储器替换算法基于不久之后不需要高速缓存行的可能性来替换高速缓存行。 根据本发明的高速缓冲存储器包括多个高速缓存行，其被相关联地访问，与存储定义替换类的计数值的每个高速缓存行相关联的计数条目。 当访问高速缓存行时，计数条目通常加载计数值，其中计数值指示即将需要高速缓存行内容的可能性。 换句话说，很快可能需要的数据被分配更高的替换类，而更具有推测性且不太可能需要的数据被分配较低的替换类。 当高速缓冲存储器变满时，替换算法选择替换具有最低替换类的那些高速缓存行。 因此，选择用于替换的高速缓存行包含尽快不太可能需要的高速缓存中最具推测性的数据。
-
公开(公告)号：US08327031B2
公开(公告)日：2012-12-04
申请号：US11054646
申请日：2005-02-08
IPC分类号： G06F15/16
CPC分类号： H04L49/65 , H04L49/109
摘要： Network devices and methods are provided involving a support chip in association with network chips. One embodiment includes a network device having a processor, a high speed interconnect, and a number of network chips coupled to one another through the high speed interconnect. The number of network chips include a conduit port which can be selectively chosen to exchange packets, received to the number of network chips, with the processor. The support chip is coupled to the number of network chips in association with selecting a conduit port on one of the number of network chips to exchange packets with the processor.
摘要翻译： 提供了涉及与网络芯片相关联的支持芯片的网络设备和方法。 一个实施例包括具有处理器，高速互连以及通过高速互连彼此耦合的多个网络芯片的网络设备。 网络芯片的数量包括可以选择性地选择以与处理器交换接收到数量的网络芯片的分组的导管端口。 支持芯片与多个网络芯片耦合，与在多个网络芯片中的一个网络芯片上选择一个导线端口，以与处理器交换分组。
-
公开(公告)号：US07894426B2
公开(公告)日：2011-02-22
申请号：US11051422
申请日：2005-02-04
IPC分类号： H04Q11/00
CPC分类号： H04L12/56
摘要： Network devices and methods are provided for device monitoring. One embodiment includes a network device having a processor, a high speed interconnect and a number of network chips. The number of network chips are coupled to one another through the high speed interconnect. The number of network chips have a conduit port which can be selectively chosen to exchange packets, received to any network chip, with the processor.
摘要翻译： 提供网络设备和方法进行设备监控。 一个实施例包括具有处理器，高速互连和多个网络芯片的网络设备。 网络芯片的数量通过高速互连彼此耦合。 网络芯片的数量具有可以选择性地选择以将接收到任何网络芯片的分组与处理器交换的导管端口。
-
公开(公告)号：US07756124B2
公开(公告)日：2010-07-13
申请号：US11088394
申请日：2005-03-23
摘要： Systems, methods, and devices are provided for moving packets on a network device. One method includes receiving packets to a number of network chips, the number of network chips having a conduit port which can be selectively chosen to exchange packets with a processor responsible for processing packets. The method includes adding data for additional functionality to certain packets. Adding data includes encapsulating the certain packets to maintain an appearance of a certain packet format.
摘要翻译： 提供系统，方法和设备用于在网络设备上移动数据包。 一种方法包括向多个网络芯片接收分组，具有导管端口的网络芯片的数量可以被选择性地选择以与负责处理分组的处理器交换分组。 该方法包括向特定数据包添加附加功能的数据。 添加数据包括封装某些数据包，以保持特定数据包格式的外观。
-
公开(公告)号：US20080298110A1
公开(公告)日：2008-12-04
申请号：US11810124
申请日：2007-06-04
申请人： John A. Wickeraad , Mark Gooch
发明人： John A. Wickeraad , Mark Gooch
IPC分类号： G11C15/04
摘要： Systems, devices, and methods, including executable instructions are provided for content addressable memory (CAM). One method includes defining the CAM into an array of data words having M rows and N columns, with each of N and M being greater than one. The data words of the CAM are arranged according to a 2-dimensional priority scheme. Data words outside a selected 1×M column are masked to be ignored in determining a match, and the CAM is searched. Each search includes N compare cycles and each compare cycle having a different 1×M column selected. A highest priority match per compare cycle is pipelined from a priority encoder with the pipelined matches arranged to communicate a priority order in a first dimension of the 2-dimensional priority scheme.
摘要翻译： 为内容可寻址存储器（CAM）提供系统，设备和方法，包括可执行指令。 一种方法包括将CAM定义为具有M行和N列的数据字阵列，其中N和M中的每一个大于1。 CAM的数据字根据二维优先级方案进行排列。 在选定的1xM列之外的数据字被屏蔽以在确定匹配时被忽略，并且搜索CAM。 每个搜索包括N个比较周期，并且选择了不同的1xM列的每个比较周期。 每个比较周期的最高优先级匹配从优先编码器流水线化，其中流水线匹配被布置为在二维优先级方案的第一维度中传送优先级顺序。
-
公开(公告)号：US07325164B2
公开(公告)日：2008-01-29
申请号：US10670620
申请日：2003-09-25
IPC分类号： G06F11/00
CPC分类号： G01R31/318522
摘要： Test circuitry is incorporated on a chip die together with a circuit to be tested, such as an ASIC or microprocessor, to provide external access to signals that are internal to an integrated circuit chip package. A controller provides the arm command and issues appropriate configuration controls to collect signal samples. In particular, a network responds to these commands from the controller to selectively provide signal samples from a device under test. A trigger event generator responds to logic or other characteristics of the signal samples to provide trigger events. These trigger events are counted by a trigger event counter in the armed state of the state machine to identify the final trigger event corresponding to an occurrence of a programmable number of the trigger events. A store event generator also responds to a programmed characteristic or combination(s) of the signal samples to provide a store event. Either or both of the event generators may use a mask to provide these events.
摘要翻译： 测试电路与要测试的电路（例如ASIC或微处理器）一起并入芯片管芯，以提供对集成电路芯片封装内部的信号的外部访问。 控制器提供arm命令并发出适当的配置控制来收集信号样本。 特别地，网络响应来自控制器的这些命令，以选择性地提供来自被测器件的信号样本。 触发事件发生器响应信号样本的逻辑或其他特性以提供触发事件。 这些触发事件由处于状态机的布防状态的触发事件计数器进行计数，以识别对应于触发事件的可编程数量的发生的最终触发事件。 存储事件发生器还响应编程的特征或信号样本的组合以提供存储事件。 事件发生器中的一个或两个可以使用掩码来提供这些事件。
-
-
-
-
-
-
-
-
-
搜索结果
32 条记录 (耗时 0.021 秒)
