公开(公告)号：US07221126B1

公开(公告)日：2007-05-22

申请号：US09561147

申请日：2000-04-28

申请人： Donald A. Williamson ,  John A. Wickeraad

发明人： Donald A. Williamson ,  John A. Wickeraad

IPC分类号： H04J3/06

CPC分类号： H04L7/0012 ,  G06F1/04 ,  G06F1/12

摘要： A method and apparatus using a clock generator with sequential logic to align the phase of a first clock generated on a receiving integrated circuit (IC) chip to a second clock received by the receiving IC chip. One embodiment of the invention involves a method for aligning the phase of a first clock relative to the phase of a second clock, wherein the first clock is provided by a clock generator in a data processing system. The method includes sampling the second clock with a sampling clock, detecting an edge on the second clock, and stretching the first clock to align the phase of the first clock relative to the phase of the second clock. A second embodiment of the invention involves a data processing system including a transmitting chip, a receiving chip, and a clock generator for aligning the phase of a first clock relative to the phase of a second clock, wherein the second clock is received by the receiving chip. The clock generator includes a sampling circuit to sample the second clock with a sampling clock, a circuit to detect an edge on the second clock, and a sequential logic circuit to stretch the first clock to align the phase of the first clock relative to the phase of the second clock and control the clock generator.

摘要翻译： 一种使用具有顺序逻辑的时钟发生器的方法和装置，用于将在接收集成电路（IC）芯片上产生的第一时钟的相位对准由接收IC芯片接收的第二时钟。 本发明的一个实施例涉及一种用于对准第一时钟相对于第二时钟的相位的方法，其中第一时钟由数据处理系统中的时钟发生器提供。 该方法包括用采样时钟采样第二时钟，检测第二时钟上的边沿，并且拉伸第一时钟以使第一时钟的相位相对于第二时钟的相位对准。 本发明的第二实施例涉及一种包括发射芯片，接收芯片和时钟发生器的数据处理系统，用于对准第一时钟相对于第二时钟的相位的相位，其中第二时钟由接收器接收 芯片。 时钟发生器包括采样电路，用采样时钟对第二时钟进行采样，检测第二时钟的边沿的电路，以及顺序逻辑电路，用于拉伸第一时钟以使第一时钟的相位相对于相位 的第二个时钟并控制时钟发生器。

公开(公告)号：US06813275B1

公开(公告)日：2004-11-02

申请号：US09556052

申请日：2000-04-21

申请人： Debendra Das Sharma ,  Donald A. Williamson ,  Edward M. Jacobs

发明人： Debendra Das Sharma ,  Donald A. Williamson ,  Edward M. Jacobs

IPC分类号： H04L1256

CPC分类号： G06F13/387 ,  H04L7/005 ,  H04L2007/045

摘要： An apparatus and method for an improved asynchronous communication channel between a transmitter and a receiver having separate clocks. The invention provides a simple implementation that solves both the overflow and the underflow problem using the same mechanism, and reduces complexity by elimination of the control split between the two clock domains. A first embodiment of the invention is a method for preventing packet underflow and packet overflow for packets sent across an asynchronous link between a transmitter and a receiver, including a buffer that can store a number of packets greater than an ideal number of packets. The method includes sending a predetermined number of drop-me warning packets and sending one or more drop-me packets from the transmitter to the receiver, receiving the predetermined number of drop-me warning packets and the one or more drop-me packets in the buffer, compensating for packet overflow when the number of packets is greater than the ideal number of packets in the buffer by skipping at least one drop-me packet, and compensating for packet underflow in the buffer when the number of packets is less than the ideal number of packets by stalling access to the buffer for one or more clock cycles. A second embodiment of the invention is an asynchronous link for packets sent between a transmitter having a first clock and a receiver having a second clock, including a buffer to receive the first clock from the transmitter and receive from the transmitter a number of packets equal to or different to a predetermined ideal number of packets, a write pointer, and a read pointer, and a read pointer control circuit to change the read pointer, wherein the buffer can receive drop-me packets, and the read pointer can skip a drop-me packet in the buffer.

摘要翻译： 一种用于在具有单独时钟的发射机和接收机之间改进的异步通信信道的装置和方法。 本发明提供了使用相同机制解决溢出和下溢问题的简单实现，并且通过消除两个时钟域之间的控制分割来降低复杂度。 本发明的第一实施例是一种用于防止在发射机和接收机之间的异步链路上发送的分组的分组下溢和分组溢出的方法，包括可以存储大于理想数目分组的分组数量的缓冲器。 该方法包括发送预定数量的丢包警告包，并从发送器发送一个或多个丢包信息包到接收器，接收预定数量的丢包警告包和一个或多个丢包信息包 缓冲器，当数据包的数量大于缓冲器中理想数量的数据包时，通过跳过至少一个丢包分组来补偿数据包溢出，并且当数据包数量小于理想值时补偿缓冲器中的数据包下溢 数据包的数量通过停止访问缓冲区一个或多个时钟周期。 本发明的第二实施例是在具有第一时钟的发射机和具有第二时钟的接收机之间发送的分组的异步链路，包括缓冲器，用于从发射机接收第一时钟，并从发射机接收等于 或者不同于预定理想数量的分组，写指针和读指针，以及读指针控制电路，以改变读指针，其中缓冲器可以接收丢包，并且读指针可以跳过下拉菜单， 我在缓冲区中的数据包。

公开(公告)号：US06598191B1

公开(公告)日：2003-07-22

申请号：US09444610

申请日：1999-11-23

申请人： Debendra Das Sharma ,  Ashish Gupta ,  Donald A. Williamson

发明人： Debendra Das Sharma ,  Ashish Gupta ,  Donald A. Williamson

IPC分类号： G01R313177

CPC分类号： G01R31/318525

摘要： A function for verifying an asynchronous boundary behavior of a digital system. The asynchronous boundary is formed at a coupling between a first series of registers clocked by a write clock (the write domain), and a second series of registers clocked by a read clock (the read domain). A delay register and multiplexer are inserted after a predetermined register within the digital system, where the predetermined register and delay register are clocked by the same clock. The output of the predetermined register is coupled to both the first input of multiplexer and a first input of the delay register. The delay register is coupled to the second input of the multiplexer. A selector is coupled to the multiplexer for selecting which of the two multiplexer inputs to pass to subsequent registers in the digital system. By inserting the delay register/multiplexer at or after the asynchronous boundary, any signal level uncertainty present between the read domain and the write domain is captured and propagated through the digital system.

摘要翻译： 用于验证数字系统的异步边界行为的功能。 异步边界形成在由写时钟（写域）计时的第一串寄存器和由读时钟（读域）计时的第二寄存器组之间的耦合上。 在数字系统中的预定寄存器之后插入延迟寄存器和多路复用器，其中预定寄存器和延迟寄存器由相同的时钟计时。 预定寄存器的输出耦合到多路复用器的第一输入端和延迟寄存器的第一输入端。 延迟寄存器耦合到多路复用器的第二输入端。 选择器耦合到多路复用器，用于选择两个多路复用器输入中的哪一个传递到数字系统中的后续寄存器。 通过在异步边界之后或之后插入延迟寄存器/多路复用器，读取域和写入域之间存在的任何信号电平不确定度被捕获并通过数字系统传播。

公开(公告)号：US4961013A

公开(公告)日：1990-10-02

申请号：US423306

申请日：1989-10-18

申请人： John R. Obermeyer, Jr. ,  John F. Shelton ,  Donald A. Williamson

发明人： John R. Obermeyer, Jr. ,  John F. Shelton ,  Donald A. Williamson

IPC分类号： G01R31/3185 ,  H03K5/15

CPC分类号： H03K5/15 ,  G01R31/318572

摘要： A scan testable circuit in a computer system is controlled by using a single scan clock and a fixed delay circuit to realize the required scan clocks and a required scan mode enable signal. The multiple signals are generated from a subset of signals supplied to the scan control signal generation circuit. System data and scan data are routed through a multiplexer to test or initialize lines and circuitry. A scan control signal generation circuit according to the invention has the advantage of eliminating as excess a scan mode enable signal originating elsewhere in the computer system, thereby eliminating unneeded signal traces while minimizing the number of pins required for this function. In a first embodiment, a scan mode enable signal is generated from one of two scan clocks. In a second embodiment, both scan clocks and the scan mode enable signal are generated from a single source clock.

摘要翻译： 通过使用单个扫描时钟和固定延迟电路来控制计算机系统中的扫描可测试电路，以实现所需的扫描时钟和所需的扫描模式使能信号。 多个信号从提供给扫描控制信号发生电路的信号的子集产生。 系统数据和扫描数据通过多路复用器进行路由，以测试或初始化线路和电路。 根据本发明的扫描控制信号产生电路具有消除作为多余的源自计算机系统其他地方的扫描模式使能信号的优点，从而消除了不需要的信号迹线，同时使该功能所需的引脚数量最小化。 在第一实施例中，从两个扫描时钟之一产生扫描模式使能信号。 在第二实施例中，从单个源时钟产生扫描时钟和扫描模式使能信号。

公开(公告)号：US4635188A

公开(公告)日：1987-01-06

申请号：US518609

申请日：1983-07-29

申请人： Donald A. Williamson ,  John F. Shelton

发明人： Donald A. Williamson ,  John F. Shelton

IPC分类号： G06F9/26 ,  G06F9/30 ,  G06F9/318 ,  G06F9/22

CPC分类号： G06F9/30145 ,  G06F9/268 ,  G06F9/3017 ,  G06F9/3889

摘要： A scheme for improving the decoding time of macroinstruction opcodes in a programmed computer is provided. By having a direct Instruction Jump Table responding to macroinstructions and a pipelined Address Jump Table responding to the same macroinstructions simultaneously, larger sequences of microinstructions are decoded in a minimum number of microcycles, thus resulting in a faster operating programmed computer.

摘要翻译： 提供了一种用于改善编程计算机中的宏指令操作码的解码时间的方案。 通过具有响应宏指令的直接指令跳转表和同时响应相同宏指令的流水线地址跳转表，较大序列的微指令以最小数量的微循环被解码，从而导致更快的操作编程计算机。