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    Reconfigurable interface for coupling functional input/output blocks to limited number of I/O pins
    2.
    发明授权
    Reconfigurable interface for coupling functional input/output blocks to limited number of I/O pins 有权
    可重构接口，用于将功能输入/输出块耦合到有限数量的I / O引脚

    公开(公告)号：US07660968B2

    公开(公告)日：2010-02-09

    申请号：US11772184

    申请日：2007-06-30

    申请人： Donald E. Alfano ,  Danny J. Allred ,  Douglas S. Piasecki ,  Kenneth W. Fernald ,  Ka Y. Leung ,  Brian Caloway ,  Alan Storvik ,  Paul Highley ,  Douglas R. Holberg

    发明人： Donald E. Alfano ,  Danny J. Allred ,  Douglas S. Piasecki ,  Kenneth W. Fernald ,  Ka Y. Leung ,  Brian Caloway ,  Alan Storvik ,  Paul Highley ,  Douglas R. Holberg

    IPC分类号： G06F13/00

    CPC分类号： G06F13/385 ,  G06F1/08 ,  G06F15/7814 ,  H03M1/122 ,  H03M1/183 ,  H03M1/462 ,  Y02D10/12 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

    摘要： A reconfigurable processor includes a processor core for operating on a set of instructions to carry out predefined processes and includes a plurality of input/output pins in addition to a plurality of functional input/output blocks. These functional blocks allow the processing core to interface with the plurality of input/output pins, each of the functional input/output blocks having an associated and predetermined functionality. This functionality comprises the output as a function of the input, the function defined by the functionality. Each of the functional input/output blocks has a requirement for a defined number of the plurality of input/output pins wherein the total of the defined number for all of the plurality of functional input/output blocks exceeds the number of the plurality of input/output pins and wherein the processor core is interfaced with one of the input or output of each of the functional blocks. A reconfigurable interface selectively interfaces between the other of the input or output of the functional blocks and a select one or ones of the plurality of input/output pins, such that the processor core can be interfaced with the select one or ones of the input/output pins. The reconfigurable interface is operable to define how each of the plurality of input/output pins interfaces with the select ones of the plurality of functional blocks and the associated functionality in accordance with configuration information. A non-volatile memory is provided for storing information for use in association with the configuration information, such that the stored information can be altered.

    摘要翻译： 可重构处理器包括用于在一组指令上操作以执行预定义的处理的处理器核心，并且除了多个功能输入/输出块之外还包括多个输入/输出引脚。 这些功能块允许处理核与多个输入/输出引脚相连接，每个功能输入/输出块具有相关联的和预定的功能。 该功能包括作为输入的功能的输出，功能定义的功能。 每个功能输入/输出块对多个输入/输出引脚的定义数量要求，其中所有多个功能输入/输出块中的所有定义数目的总数超过多个输入/ 输出引脚，并且其中处理器核心与每个功能块的输入或输出中的一个接口。 可重配置接口选择性地在功能块的输入或输出中的另一个与多个输入/输出引脚中的选择一个或多个输入/输出引脚之间进行接口，使得处理器核可以与选择的一个或多个输入/ 输出引脚。 可重配置接口可操作以根据配置信息定义多个输入/输出引脚中的每一个如何与多个功能块中的选择功能块和相关联的功能接口。 提供非易失性存储器用于存储与配置信息相关联使用的信息，使得可以改变所存储的信息。

    Priority cross-bar decoder
    5.
    发明授权
    Priority cross-bar decoder 有权
    优先交叉条解码器

    公开(公告)号：US06839795B1

    公开(公告)日：2005-01-04

    申请号：US09584308

    申请日：2000-05-31

    申请人： Kenneth W. Fernald ,  Danny J. Allred ,  Donald E. Alfano

    发明人： Kenneth W. Fernald ,  Danny J. Allred ,  Donald E. Alfano

    IPC分类号： H04Q3/52 ,  G06F13/00

    CPC分类号： H04Q3/52 ,  H04Q2213/1302 ,  H04Q2213/1304 ,  H04Q2213/13103 ,  H04Q2213/1325

    摘要： A matrix of routing cells forming a cross-bar decoder (70). Signal triplets (84, 86, 88) coupled to the cross-bar decoder (70) are assigned a priority. A register (50) provide outputs to the cross-bar decoder (70) to either activate or deactivate routing of the triplet signals (84, 86,88) through the cross-bar decoder (70). The routing cells (72-82) are arranged in a matrix of columns and rows, where the triplet signals are applied to the row routing cells (72, 74, 76) and are extracted at the column routing cells (76, 80, 82). When a routing cell in a row is enabled to couple signals to an output, it disables all other lower priority routing cells in its column so that they cannot route signals to that output. Based on the automatic disabling of routing cells by others, the signals ripple through the cross-bar decoder (70) until all high priority I/O pins are used. The outputs of the cross-bar decoder (70) are coupled to respective I/O pins (170, 172, 174) by way of respective driver circuits (212, 216, 236).

    摘要翻译： 形成交叉条形码解码器（70）的路由信元的矩阵。 耦合到交叉条形码解码器（70）的信号三元组（84,86,88）被赋予优先权。 寄存器（50）向交叉条形码解码器（70）提供输出以通过交叉条形码解码器（70）来激活或去激活三联信号（84,88,88）的路由。 路由单元（72-82）被布置成列和行的矩阵，其中三元组信号被施加到行路由单元（72,74,76），并且在列路由单元（76,80,82）处被提取 ）。 当一行中的路由单元被使能以将信号耦合到输出时，它将禁用其列中的所有其他较低优先级的路由单元，使得它们不能将信号路由到该输出。 基于其他路由单元的自动禁用，通过交叉条形码解码器（70）的信号直到所有高优先级I / O引脚使用。 横杆解码器（70）的输出通过相应的驱动器电路（212,216,236）耦合到相应的I / O引脚（170,172,174）。