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17 条记录 (耗时 0.168 秒)

    Reconfigurable interface for coupling functional input/output blocks to limited number of I/O pins
    2.
    发明授权
    Reconfigurable interface for coupling functional input/output blocks to limited number of I/O pins 有权
    可重构接口，用于将功能输入/输出块耦合到有限数量的I / O引脚

    公开(公告)号：US07660968B2

    公开(公告)日：2010-02-09

    申请号：US11772184

    申请日：2007-06-30

    申请人： Donald E. Alfano ,  Danny J. Allred ,  Douglas S. Piasecki ,  Kenneth W. Fernald ,  Ka Y. Leung ,  Brian Caloway ,  Alan Storvik ,  Paul Highley ,  Douglas R. Holberg

    发明人： Donald E. Alfano ,  Danny J. Allred ,  Douglas S. Piasecki ,  Kenneth W. Fernald ,  Ka Y. Leung ,  Brian Caloway ,  Alan Storvik ,  Paul Highley ,  Douglas R. Holberg

    IPC分类号： G06F13/00

    CPC分类号： G06F13/385 ,  G06F1/08 ,  G06F15/7814 ,  H03M1/122 ,  H03M1/183 ,  H03M1/462 ,  Y02D10/12 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

    摘要： A reconfigurable processor includes a processor core for operating on a set of instructions to carry out predefined processes and includes a plurality of input/output pins in addition to a plurality of functional input/output blocks. These functional blocks allow the processing core to interface with the plurality of input/output pins, each of the functional input/output blocks having an associated and predetermined functionality. This functionality comprises the output as a function of the input, the function defined by the functionality. Each of the functional input/output blocks has a requirement for a defined number of the plurality of input/output pins wherein the total of the defined number for all of the plurality of functional input/output blocks exceeds the number of the plurality of input/output pins and wherein the processor core is interfaced with one of the input or output of each of the functional blocks. A reconfigurable interface selectively interfaces between the other of the input or output of the functional blocks and a select one or ones of the plurality of input/output pins, such that the processor core can be interfaced with the select one or ones of the input/output pins. The reconfigurable interface is operable to define how each of the plurality of input/output pins interfaces with the select ones of the plurality of functional blocks and the associated functionality in accordance with configuration information. A non-volatile memory is provided for storing information for use in association with the configuration information, such that the stored information can be altered.

    摘要翻译： 可重构处理器包括用于在一组指令上操作以执行预定义的处理的处理器核心，并且除了多个功能输入/输出块之外还包括多个输入/输出引脚。 这些功能块允许处理核与多个输入/输出引脚相连接，每个功能输入/输出块具有相关联的和预定的功能。 该功能包括作为输入的功能的输出，功能定义的功能。 每个功能输入/输出块对多个输入/输出引脚的定义数量要求，其中所有多个功能输入/输出块中的所有定义数目的总数超过多个输入/ 输出引脚，并且其中处理器核心与每个功能块的输入或输出中的一个接口。 可重配置接口选择性地在功能块的输入或输出中的另一个与多个输入/输出引脚中的选择一个或多个输入/输出引脚之间进行接口，使得处理器核可以与选择的一个或多个输入/ 输出引脚。 可重配置接口可操作以根据配置信息定义多个输入/输出引脚中的每一个如何与多个功能块中的选择功能块和相关联的功能接口。 提供非易失性存储器用于存储与配置信息相关联使用的信息，使得可以改变所存储的信息。

    Digital control circuit for switching power supply with serial data input
    6.
    发明授权
    Digital control circuit for switching power supply with serial data input 有权
    数字控制电路，用于串行数据输入开关电源

    公开(公告)号：US07492139B2

    公开(公告)日：2009-02-17

    申请号：US11382462

    申请日：2006-05-09

    申请人： Donald E. Alfano ,  Paul Highley ,  Kenneth W. Fernald

    发明人： Donald E. Alfano ,  Paul Highley ,  Kenneth W. Fernald

    IPC分类号： G05F1/40

    CPC分类号： H02M3/33576 ,  H02M3/33515

    摘要： A method is disclosed for converting DC power from a first voltage level on an input to a different voltage level on an output for delivery to a load. The method includes switching current in a switching operation from the input to the output through an inductive element and measuring the voltage/current parameters on the input and output. A control algorithm is then utilized to determine control parameters necessary to make a control move to effect the switching operation, the control algorithm utilizing as inputs the measured voltage/current parameters. A digital control system controls the switching operation, which digital control system is operable to be controlled by the control algorithm. Configuration data is received on a serial data bus for configuring the control algorithm. Thereafter, the operation of the control algorithm is modified in response to receiving the configuration information.

    摘要翻译： 公开了一种用于将DC功率从输入端的第一电压电平转换为输出到输出的输出上的不同电压电平的方法。 该方法包括通过电感元件将开关操作中的电流从输入切换到输出，并测量输入和输出上的电压/电流参数。 然后利用控制算法来确定使控制移动以实现开关操作所必需的控制参数，该控制算法利用测量的电压/电流参数作为输入。 数字控制系统控制切换操作，数字控制系统可操作地由控制算法控制。 在串行数据总线上接收配置数据，以配置控制算法。 此后，响应于接收到配置信息来修改控制算法的操作。

    Digital control circuit for switching power supply with pattern generator
    7.
    发明授权
    Digital control circuit for switching power supply with pattern generator 失效
    用模式发生器切换电源的数字控制电路

    公开(公告)号：US07042201B2

    公开(公告)日：2006-05-09

    申请号：US10742509

    申请日：2003-12-19

    申请人： Donald E. Alfano ,  Paul Highley ,  Kenneth W. Fernald

    发明人： Donald E. Alfano ,  Paul Highley ,  Kenneth W. Fernald

    IPC分类号： G05F1/40

    CPC分类号： H02M3/33576 ,  H02M3/33515

    摘要： Digital control circuit for switching power supply with pattern generator. A method is disclosed for converting DC power from a first voltage level on an input to a different voltage level on an output for delivery to a load. Current from the input is switched to the output through an inductive element with a plurality of switches, each of the switches driven by a waveform, all of the waveforms driving the switches referenced with a predetermined relationship to a master clock and all operating on a PWM duty cycle of the master clock. The voltage/current parameters on the input and output are measured and then a control algorithm is utilized to determine a change in the PWM duty cycle necessary to make a control move, the control algorithm utilizing as inputs the measured voltage/current parameters. A pre-stored waveform pattern for each of the waveforms is then modified to reflect the change in the PWM duty cycle required for the control move. After modification, the modified pattern is output to create the waveform and drive the respective switches.

    摘要翻译： 用模式发生器切换电源的数字控制电路。 公开了一种用于将DC功率从输入端的第一电压电平转换为输出到输出的输出上的不同电压电平的方法。 来自输入的电流通过具有多个开关的电感元件切换到输出，每个开关由波形驱动，驱动开关的所有波形以与主时钟预定的关系为参考，并且全部在PWM上工作 主时钟的占空比。 测量输入和输出上的电压/电流参数，然后使用控制算法来确定进行控制移动所需的PWM占空比的变化，该控制算法利用测量的电压/电流参数作为输入。 然后对每个波形的预先存储的波形图进行修改，以反映控制移动所需的PWM占空比的变化。 修改后，输出修改后的图案，创建波形并驱动各个开关。

    Method and apparatus for calibration of a low frequency oscillator in a processor based system
    8.
    发明授权
    Method and apparatus for calibration of a low frequency oscillator in a processor based system 有权
    用于在基于处理器的系统中校准低频振荡器的方法和装置

    公开(公告)号：US07250825B2

    公开(公告)日：2007-07-31

    申请号：US10865110

    申请日：2004-06-10

    申请人： Brent Wilson ,  Paul Highley ,  Kenneth W. Fernald

    发明人： Brent Wilson ,  Paul Highley ,  Kenneth W. Fernald

    IPC分类号： G01R23/10 ,  H03I1/00

    CPC分类号： H03L7/08 ,  H03L1/02

    摘要： Method and apparatus for calibration of a low frequency oscillator in a processor based system. A method for calibrating an on-chip non-precision oscillator. An on-chip precision oscillator is provided having a known frequency of operation that is within an acceptable operating tolerance. The on-chip precision oscillator is used as a time base and then the period of the on-chip oscillator is measured as a function of the time base. The difference between the measured frequency of the on-chip non-precision oscillator and a desired operating frequency of the on-chip non-precision oscillator is then determined. After the difference is determined, the frequency of the on-chip non-precision oscillator is adjusted to minimize the determined difference.

    摘要翻译： 用于在基于处理器的系统中校准低频振荡器的方法和装置。 一种用于校准片上非精密振荡器的方法。 提供具有在可接受的工作公差内的已知操作频率的片上精密振荡器。 片上精密振荡器用作时基，然后根据时基测量片上振荡器的周期。 然后确定片上非精密振荡器的测量频率与片上非精密振荡器的期望工作频率之间的差异。 在确定差异之后，调整片上非精密振荡器的频率以使确定的差最小化。

    Method and apparatus for accessing paged memory with indirect addressing
    9.
    发明授权
    Method and apparatus for accessing paged memory with indirect addressing 失效
    用间接寻址访问分页存储器的方法和装置

    公开(公告)号：US06886089B2

    公开(公告)日：2005-04-26

    申请号：US10295585

    申请日：2002-11-15

    申请人： Kenneth W. Fernald ,  Alvin C. Storvik, II ,  Paul Highley ,  Brent Wilson

    发明人： Kenneth W. Fernald ,  Alvin C. Storvik, II ,  Paul Highley ,  Brent Wilson

    IPC分类号： G06F12/00 ,  G06F12/06

    CPC分类号： G06F12/063

    摘要： Method and apparatus for accessing paged memory with indirect addressing. A a method for changing pages of memory in an indirect addressed memory having a plurality of addressable locations therein is diclosed. An index indicative of the page of the memory being addressed is stored in a memory location. The memory is addressed with a direct address that selects one or more of the addressable locations in the addressed page of memory. An interrupt is received from a resource capable of generating an interrupt, which interrupt has associated therewith a defined one of the pages of memory. In response to generation of the interrupt, the value of the stored index t is changed o an index associated with the defined one of the pages of memory associated with the resource. In response to receiving a signal indicative of the generated interrupt having been serviced by a system that services interrupts, the stored index is changed to a different index.

    摘要翻译： 用间接寻址访问分页存储器的方法和装置。 一种在其中具有多个可寻址位置的间接寻址存储器中改变存储器页面的方法是关闭的。 指示被寻址的存储器的页面的索引被存储在存储器位置中。 存储器通过选择存储器寻址页面中的一个或多个可寻址位置的直接地址来寻址。 从能够产生中断的资源接收到中断，该中断与其中定义的一个存储器页面相关联。 响应于中断的产生，存储的索引t的值被改变为与与资源相关联的所定义的一个存储器页面相关联的索引。 响应于接收到指示已经由服务中断的系统服务的所产生的中断的信号，所存储的索引被改变为不同的索引。

    Paging scheme for a microcontroller for extending available register space
    10.
    发明授权
    Paging scheme for a microcontroller for extending available register space 有权
    用于扩展可用寄存器空间的微控制器的寻呼方案

    公开(公告)号：US06898689B2

    公开(公告)日：2005-05-24

    申请号：US10295721

    申请日：2002-11-15

    申请人： Alvin C. Storvik, II ,  Kenneth W. Fernald ,  Paul Highley ,  Brent Wilson

    发明人： Alvin C. Storvik, II ,  Kenneth W. Fernald ,  Paul Highley ,  Brent Wilson

    IPC分类号： G06F12/06 ,  G06F12/00

    CPC分类号： G06F12/063

    摘要： Paging scheme for a microcontroller for extending available register space. A method for paging at least a portion of an address space in a processing system is disclosed. A plurality of addressable memory locations are provided arranged in pages. Each of the addressable memory locations in each of the pages occupies at least a portion of the address space of the processing system and has an associated address in the address space of the processing system. A page pointer is stored in a storage location to define the desired page and then an address is generated in the at least a portion of the address space of the processing system. At least one of the addressable memory locations in at least two of the pages with the same address has identical information stored therein. The one of the addressable memory locations associated with both the generated address in the at least a portion of the address space in the processing system and the page pointer is then accessed

    摘要翻译： 用于扩展可用寄存器空间的微控制器的寻呼方案。 公开了一种用于在处理系统中寻呼地址空间的至少一部分的方法。 多页可寻址存储器位置被设置成页面。 每个页面中的每个可寻址存储器位置占据处理系统的地址空间的至少一部分，并且在处理系统的地址空间中具有相关联的地址。 页面指​​针存储在存储位置中以定义所需页面，然后在处理系统的地址空间的至少一部分中生成地址。 具有相同地址的至少两个页面中的可寻址存储器位置中的至少一个具有存储在其中的相同信息。 然后访问与处理系统中的地址空间的至少一部分中的生成地址和页指针相关联的可寻址存储器位置之一