公开(公告)号：US06895494B1

公开(公告)日：2005-05-17

申请号：US09603226

申请日：2000-06-26

申请人： Donald E. Steiss ,  Laurence Ray Simar, Jr.

发明人： Donald E. Steiss ,  Laurence Ray Simar, Jr.

IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F15/00

CPC分类号： G06F9/30174 ,  G06F9/30196 ,  G06F9/3822 ,  G06F9/3853

摘要： A subpipelined translation embodiment provides binary compatibility between current an future generations of DSPs. When retrieved from memory an entire fetch packet is assigned an operating mode (base instruction set or migrant instruction set) according to the current execution mode. The fetch packets from the instruction memory are parsed into execute packets and sorted by execution unit (dispatched) in a datapath shared by both execution modes (base and migrant). The two execution modes have separate control logic. Instructions from the dispatch datapath are decoded by either base architecture decode logic or the migrant architecture decode logic, depending on the execution mode bound to the parent fetch packet. Code processed by the migrant and base decode pipelines produces machine words that are selected by a multiplexer. The multiplexer is controlled by the operating mode bound to the fetch packet that produced the machine word. The selected machine word controls a global register file, which supplies operands to all hardware execution units and accepts results of all hardware execution units.

摘要翻译： 辅助翻译实施例提供了当前未来几代DSP之间的二进制兼容性。 当根据当前的执行模式从存储器检索到整个获取数据包的操作模式（基本指令集或迁移指令集）。 来自指令存储器的获取数据包被解析为执行数据包，并由执行单元（分派）按照两个执行模式（基础和移植）共享的数据路径进行排序。 这两种执行模式具有单独的控制逻辑。 根据绑定到父提取数据包的执行模式，调度数据路径的指令由基础架构解码逻辑或移植体架构解码逻辑进行解码。 由移动和基本解码管线处理的代码产生由多路复用器选择的机器字。 多路复用器由绑定到产生机器字的提取数据包的操作模式控制。 所选的机器字控制一个全局寄存器文件，其向所有硬件执行单元提供操作数，并接受所有硬件执行单元的结果。

公开(公告)号：US5964825A

公开(公告)日：1999-10-12

申请号：US598775

申请日：1996-02-09

申请人： Nat Seshan ,  Laurence Ray Simar, Jr.

发明人： Nat Seshan ,  Laurence Ray Simar, Jr.

IPC分类号： G06F9/30 ,  G06F9/302 ,  G06F9/32 ,  G06F9/38 ,  G06F7/38

CPC分类号： G06F9/30094 ,  G06F9/3001 ,  G06F9/30072 ,  G06F9/30101

摘要： A general purpose microprocessor architecture enabling more efficient computations of a type in which Boolean operations and arithmetic operations conditioned on the results of the Boolean operations are interleaved. The microprocessor is provided with a plurality of general purpose registers ("GPRs" 102) and an arithmetic logic unit ("ALU" 104), capable of performing arithmetic operations and comparison operations. The ALU has a first input (108) and a second input (110), and an output (112), the first and second inputs receiving values stored in the GPRs. The output stores the results of the arithmetic logic unit operations in the GPRs. At least one of the GPRs is capable of receiving directly from the ALU a result of a Boolean operation. In one embodiment, at least one of the GPRs (PN) capable of receiving directly from the ALU a result of a Boolean operation is configured so as to cause the conditioning of an arithmetic operation of the ALU based on the value stored in the GPR.

摘要翻译： 一种通用的微处理器架构，能够更有效地计算一种类型，其中布尔运算和运算布置运算结果的算术运算被交错。 微处理器具有能够执行算术运算和比较运算的多个通用寄存器（“GPR”102）和算术逻辑单元（“ALU”104）。 ALU具有第一输入（108）和第二输入（110）以及输出（112），第一和第二输入接收存储在GPR中的值。 输出将算术逻辑单元操作的结果存储在GPR中。 至少有一个GPR能够直接从ALU接收布尔运算的结果。 在一个实施例中，能够直接从ALU接收到布尔运算结果的至少一个GPR（PN）被配置成基于存储在GPR中的值来调节ALU的算术运算。

公开(公告)号：US07886255B2

公开(公告)日：2011-02-08

申请号：US12017503

申请日：2008-01-22

申请人： Laurence Ray Simar, Jr. ,  Reid E. Tatge

发明人： Laurence Ray Simar, Jr. ,  Reid E. Tatge

IPC分类号： G06F17/50

CPC分类号： G06F15/7867 ,  G06F17/5045

摘要： A method of integrated circuit programmed data processor design includes selecting a benchmark application, selecting an initial set of architecture parameters, reconfiguring a compiler for the selected architecture parameters, compiling the benchmark, reconfiguring a data processor simulator to the selected architecture parameters, running the complied benchmark on the reconfigured simulator, automatically synthesizing an integrated circuit physical layout and evaluating performance of the selected architecture parameters against predetermined criteria. The method varies the selected architecture parameters upon failure to meet criteria until evaluation of the selected architecture parameters meets the criteria. The method selects a number of datapath clusters to avoid too many input/output ports in data registers.

摘要翻译： 集成电路编程数据处理器设计的方法包括选择基准应用程序，选择初始的架构参数集合，针对所选择的架构参数重新配置编译器，编译基准，将数据处理器模拟器重新配置为选定的架构参数，运行已编译的 在重新配置的仿真器上进行基准测试，根据预定标准自动合成集成电路物理布局并评估所选体系结构参数的性能。 该方法在不符合标准的情况下改变所选择的架构参数，直到所选择的架构参数的评估满足标准。 该方法选择多个数据路径集群，以避免数据寄存器中输入/输出端口太多。