公开(公告)号：US07191368B1

公开(公告)日：2007-03-13

申请号：US09938157

申请日：2001-08-22

申请人： Donald V. Organ ,  Kenneth J. Lanier ,  Roger W. Blethen ,  H. Neil Kelly ,  Michael G. Davis ,  Jeffrey H. Perkins ,  Tommie Berry ,  Phillip Burlison ,  Mark Deome ,  Christopher J. Hannaford ,  Edward J. Terrenzi ,  David Menis ,  David W. Curry ,  Eric Rosenfeld

发明人： Donald V. Organ ,  Kenneth J. Lanier ,  Roger W. Blethen ,  H. Neil Kelly ,  Michael G. Davis ,  Jeffrey H. Perkins ,  Tommie Berry ,  Phillip Burlison ,  Mark Deome ,  Christopher J. Hannaford ,  Edward J. Terrenzi ,  David Menis ,  David W. Curry ,  Eric Rosenfeld

IPC分类号： G06F11/00

CPC分类号： G01R1/025 ,  G01R31/2834 ,  G01R31/319

摘要： An electronic tester with digital, and analog, and memory test circuitry on a single platform. A test head is coupled to a device under test. The device under test can be a system-on-a-chip integrated circuit, a mixed signal integrated circuit, a digital integrated circuit, or an analog integrated circuit. Digital test circuitry applies digital test signals to the device under test coupled to the test head and receives digital outputs from the device under test in response to the digital test signals. Analog test circuitry applies analog test signals to the device under test coupled to the test head and receives analog outputs from the device under test in response to the analog test signals. Memory test circuitry applies memory test patterns to the device under test coupled to the test head and receives memory outputs from the device under test in response to the memory test patterns. A tester computer supervises the application of digital, analog, and memory test signals from the digital, analog, and memory test circuitry to the device under test such that signals applied to the device under test can be solely digital test signals, solely analog test signals, solely memory test signals, or mixed digital, analog, and memory test signals. The test head, the digital test circuitry, the analog test circuitry, the memory test circuitry, and the computer are operable as a single platform.

摘要翻译： 一个电子测试仪，在单个平台上具有数字，模拟和内存测试电路。 测试头耦合到被测设备。 被测器件可以是片上系统集成电路，混合信号集成电路，数字集成电路或模拟集成电路。 数字测试电路将数字测试信号应用于与测试头相连的被测器件，并响应于数字测试信号接收来自被测器件的数字输出。 模拟测试电路将模拟测试信号应用于与测试头耦合的待测器件，并根据模拟测试信号接收来自被测器件的模拟输出。 存储器测试电路将内存测试模式应用到与测试头耦合的待测器件，并响应于存储器测试模式接收来自被测器件的存储器输出。 测试计算机监控从数字，模拟和存储器测试电路到被测器件的数字，模拟和存储器测试信号的应用，使得施加到被测器件的信号可以是单独的数字测试信号，只有模拟测试信号 ，单独记忆测试信号，或混合数字，模拟和存储器测试信号。 测试头，数字测试电路，模拟测试电路，存储器测试电路和计算机可操作为单个平台。

公开(公告)号：US06449741B1

公开(公告)日：2002-09-10

申请号：US09183038

申请日：1998-10-30

申请人： Donald V. Organ ,  Kenneth J. Lanier ,  Roger W. Blethen ,  H. Neil Kelly ,  Michael G. Davis ,  Jeffrey H. Perkins ,  Tommie Berry ,  Phillip Burlison ,  Mark Deome ,  Christopher J. Hannaford ,  Edward J. Terrenzi ,  David Menis ,  David W. Curry ,  Eric Rosenfeld

发明人： Donald V. Organ ,  Kenneth J. Lanier ,  Roger W. Blethen ,  H. Neil Kelly ,  Michael G. Davis ,  Jeffrey H. Perkins ,  Tommie Berry ,  Phillip Burlison ,  Mark Deome ,  Christopher J. Hannaford ,  Edward J. Terrenzi ,  David Menis ,  David W. Curry ,  Eric Rosenfeld

IPC分类号： H02H305

CPC分类号： G01R1/025 ,  G01R31/2834 ,  G01R31/319

摘要： An electronic tester with digital, and analog, and memory test circuitry on a single platform. A test head is coupled to a device under test. The device under test can be a system-on-a-chip integrated circuit, a mixed signal integrated circuit, a digital integrated circuit, or an analog integrated circuit. Digital test circuitry applies digital test signals to the device under test coupled to the test head and receives digital outputs from the device under test in response to the digital test signals. Analog test circuitry applies analog test signals to the device under test coupled to the test head and receives analog outputs from the device under test in response to the analog test signals. Memory test circuitry applies memory test patterns to the device under test coupled to the test head and receives memory outputs from the device under test in response to the memory test patterns. A tester computer supervises the application of digital, analog, and memory test signals from the digital, analog, and memory test circuitry to the device under test such that signals applied to the device under test can be solely digital test signals, solely analog test signals, solely memory test signals, or mixed digital, analog, and memory test signals. The test head, the digital test circuitry, the analog test circuitry, the memory test circuitry, and the computer are operable as a single platform.

摘要翻译： 一个电子测试仪，在单个平台上具有数字，模拟和内存测试电路。 测试头耦合到被测设备。 被测器件可以是片上系统集成电路，混合信号集成电路，数字集成电路或模拟集成电路。 数字测试电路将数字测试信号应用于与测试头相连的被测器件，并响应于数字测试信号接收来自被测器件的数字输出。 模拟测试电路将模拟测试信号应用于与测试头耦合的待测器件，并根据模拟测试信号接收来自被测器件的模拟输出。 存储器测试电路将内存测试模式应用到与测试头耦合的待测器件，并响应于存储器测试模式接收来自被测器件的存储器输出。 测试计算机监控从数字，模拟和存储器测试电路到被测器件的数字，模拟和存储器测试信号的应用，使得施加到被测器件的信号可以是单独的数字测试信号，只有模拟测试信号 ，单独记忆测试信号，或混合数字，模拟和存储器测试信号。 测试头，数字测试电路，模拟测试电路，存储器测试电路和计算机可操作为单个平台。

公开(公告)号：US06675339B1

公开(公告)日：2004-01-06

申请号：US09935453

申请日：2001-08-22

申请人： Kenneth J. Lanier ,  Roger W. Blethen ,  H. Neil Kelly ,  Michael G. Davis ,  Jeffrey H. Perkins ,  Tommie Berry ,  Phillip Burlison ,  Mark Deome ,  Christopher J. Hannaford ,  Edward J. Terrenzi ,  David Menis ,  David W. Curry ,  Eric Rosenfeld

发明人： Kenneth J. Lanier ,  Roger W. Blethen ,  H. Neil Kelly ,  Michael G. Davis ,  Jeffrey H. Perkins ,  Tommie Berry ,  Phillip Burlison ,  Mark Deome ,  Christopher J. Hannaford ,  Edward J. Terrenzi ,  David Menis ,  David W. Curry ,  Eric Rosenfeld

IPC分类号： G01R3128

CPC分类号： G01R1/025 ,  G01R31/2834 ,  G01R31/319

摘要： An electronic tester with digital, and analog, and memory test circuitry on a single platform. A test head is coupled to a device under test. The device under test can be a system-on-a-chip integrated circuit, a mixed signal integrated circuit, a digital integrated circuit, or an analog integrated circuit. Digital test circuitry applies digital test signals to the device under test coupled to the test head and receives digital outputs from the device under test in response to the digital test signals. Analog test circuitry applies analog test signals to the device under test coupled to the test head and receives analog outputs from the device under test in response to the analog test signals. Memory test circuitry applies memory test patters to the device under test coupled to the test head and receives memory outputs from the device under test in response to the memory test patterns. A tester computer supervises the application of digital, analog, and memory test signals from the digital, analog, and memory test circuitry to the device under test such that signals applied to the device under test can be solely digital test signals, solely analog test signals, solely memory test signals, or mixed digital, analog, and memory test signals. The test head, the digital test circuitry, the analog test circuitry, the memory test circuitry, and the computer are operable as a single platform.

摘要翻译： 一个电子测试仪，在单个平台上具有数字，模拟和内存测试电路。 测试头耦合到被测设备。 被测器件可以是片上系统集成电路，混合信号集成电路，数字集成电路或模拟集成电路。 数字测试电路将数字测试信号应用于与测试头相连的被测器件，并响应于数字测试信号接收来自被测器件的数字输出。 模拟测试电路将模拟测试信号应用于与测试头耦合的待测器件，并根据模拟测试信号接收来自被测器件的模拟输出。 存储器测试电路将存储器测试图案应用于被测器件，耦合到测试头，并响应于存储器测试模式接收来自被测器件的存储器输出。 测试计算机监控从数字，模拟和存储器测试电路到被测器件的数字，模拟和存储器测试信号的应用，使得施加到被测器件的信号可以是单独的数字测试信号，只有模拟测试信号 ，单独记忆测试信号，或混合数字，模拟和存储器测试信号。 测试头，数字测试电路，模拟测试电路，存储器测试电路和计算机可操作为单个平台。

公开(公告)号：US07092837B1

公开(公告)日：2006-08-15

申请号：US10663469

申请日：2003-09-15

申请人： Kenneth J. Lanier ,  Roger W. Blethen ,  H. Neil Kelly ,  Michael G. Davis ,  Jeffrey H. Perkins ,  Tommie Berry ,  Phillip Burlison ,  Mark Deome ,  Christopher J. Hannaford ,  Edward J. Terrenzi ,  David Menis ,  David W. Curry ,  Eric Rosenfeld

发明人： Kenneth J. Lanier ,  Roger W. Blethen ,  H. Neil Kelly ,  Michael G. Davis ,  Jeffrey H. Perkins ,  Tommie Berry ,  Phillip Burlison ,  Mark Deome ,  Christopher J. Hannaford ,  Edward J. Terrenzi ,  David Menis ,  David W. Curry ,  Eric Rosenfeld

IPC分类号： G06F1/06

CPC分类号： G01R31/31903 ,  G11C29/56 ,  G11C2029/5602

摘要： An electronic tester with digital, and analog, and memory test circuitry on a single platform. A test head is coupled to a device under test. The device under test can be a system-on-a-chip integrated circuit, a mixed signal integrated circuit, a digital integrated circuit, or an analog integrated circuit. Digital test circuitry applies digital test signals to the device under test coupled to the test head and receives digital outputs from the device under test in response to the digital test signals. Analog test circuitry applies analog test signals to the device under test coupled to the test head and receives analog outputs from the device under test in response to the analog test signals. Memory test circuitry applies memory test patterns to the device under test coupled to the test head and receives memory outputs from the device under test in response to the memory test patterns. A tester computer supervises the application of digital, analog, and memory test signals from the digital, analog, and memory test circuitry to the device under test such that signals applied to the device under test can be solely digital test signals, solely analog test signals, solely memory test signals, or mixed digital, analog, and memory test signals. The test head, the digital test circuitry, the analog test circuitry, the memory test circuitry, and the computer are operable as a single platform.