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公开(公告)号：US07191368B1
公开(公告)日：2007-03-13
申请号：US09938157
申请日：2001-08-22
申请人： Donald V. Organ , Kenneth J. Lanier , Roger W. Blethen , H. Neil Kelly , Michael G. Davis , Jeffrey H. Perkins , Tommie Berry , Phillip Burlison , Mark Deome , Christopher J. Hannaford , Edward J. Terrenzi , David Menis , David W. Curry , Eric Rosenfeld
发明人： Donald V. Organ , Kenneth J. Lanier , Roger W. Blethen , H. Neil Kelly , Michael G. Davis , Jeffrey H. Perkins , Tommie Berry , Phillip Burlison , Mark Deome , Christopher J. Hannaford , Edward J. Terrenzi , David Menis , David W. Curry , Eric Rosenfeld
IPC分类号： G06F11/00
CPC分类号： G01R1/025 , G01R31/2834 , G01R31/319
摘要： An electronic tester with digital, and analog, and memory test circuitry on a single platform. A test head is coupled to a device under test. The device under test can be a system-on-a-chip integrated circuit, a mixed signal integrated circuit, a digital integrated circuit, or an analog integrated circuit. Digital test circuitry applies digital test signals to the device under test coupled to the test head and receives digital outputs from the device under test in response to the digital test signals. Analog test circuitry applies analog test signals to the device under test coupled to the test head and receives analog outputs from the device under test in response to the analog test signals. Memory test circuitry applies memory test patterns to the device under test coupled to the test head and receives memory outputs from the device under test in response to the memory test patterns. A tester computer supervises the application of digital, analog, and memory test signals from the digital, analog, and memory test circuitry to the device under test such that signals applied to the device under test can be solely digital test signals, solely analog test signals, solely memory test signals, or mixed digital, analog, and memory test signals. The test head, the digital test circuitry, the analog test circuitry, the memory test circuitry, and the computer are operable as a single platform.
摘要翻译： 一个电子测试仪，在单个平台上具有数字，模拟和内存测试电路。 测试头耦合到被测设备。 被测器件可以是片上系统集成电路，混合信号集成电路，数字集成电路或模拟集成电路。 数字测试电路将数字测试信号应用于与测试头相连的被测器件，并响应于数字测试信号接收来自被测器件的数字输出。 模拟测试电路将模拟测试信号应用于与测试头耦合的待测器件，并根据模拟测试信号接收来自被测器件的模拟输出。 存储器测试电路将内存测试模式应用到与测试头耦合的待测器件，并响应于存储器测试模式接收来自被测器件的存储器输出。 测试计算机监控从数字，模拟和存储器测试电路到被测器件的数字，模拟和存储器测试信号的应用，使得施加到被测器件的信号可以是单独的数字测试信号，只有模拟测试信号 ，单独记忆测试信号，或混合数字，模拟和存储器测试信号。 测试头，数字测试电路，模拟测试电路，存储器测试电路和计算机可操作为单个平台。
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公开(公告)号：US4376385A
公开(公告)日：1983-03-15
申请号：US190633
申请日：1980-09-24
申请人： Michael G. Davis
发明人： Michael G. Davis
CPC分类号： B23K11/31 , B21D1/06 , Y10S72/705
摘要： A tool for recontouring metal such as dents in the body of an automobile, for use in conjunction with an electrical welding apparatus, including a shaft on which a weight reciprocates, the weight being permitted to selectively collide with structure provided by the shaft to impart a force to the shaft along the longitudinal axis thereof, a portion of the shaft being electrically conductive and electrically connected to the electrical welding apparatus, the electrically conductive portion of the shaft for contacting the metal surface to be straightened, activation of the electrical welding apparatus welding the electrically conductive portion of the shaft to the surface to be straightened so that the forces transferred to the shaft by the weight can act upon the surface to be straightened. One embodiment of the present invention is configured to cooperate with the electrode provided by commercial electrical welding apparatuses while a second embodiment shows a configuration for wiring the tool directly to a cable which in turn can be connected to various types of welding apparatuses.
摘要翻译： 一种用于重新配合汽车车身中的金属如凹痕的工具，用于与电焊设备结合使用，电焊设备包括一个重量往复运动的轴，该重量被允许与该轴提供的结构选择性碰撞， 所述轴的一部分导电并电连接到所述电焊装置，所述轴的导电部分用于接触要拉直的所述金属表面，所述电焊装置焊接的启动 轴的导电部分到要矫直的表面，使得由重物传递到轴的力可以作用在要被矫直的表面上。 本发明的一个实施例被配置为与由商用电焊设备提供的电极配合，而第二实施例示出了将工具直接连接到电缆的配置，电缆又可连接到各种类型的焊接设备。
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3.发明授权Communications headset with universally adaptable receiver and voice transmitter 失效通信耳机具有普遍适用的接收机和语音发射机
公开(公告)号：US5761298A
公开(公告)日：1998-06-02
申请号：US658838
申请日：1996-05-31
CPC分类号： H04R1/1066 , H04M1/05 , H04R1/08 , H04R1/1016 , H04R1/105 , H04R2201/107 , H04R2201/109
摘要： A communications headset includes a headset enclosure and a receiver enclosure coupled thereto by various means allowing displacement of the receiver enclosure with respect to the headset enclosure at any of a variety of angles, rotations, and distances. The adaptable positioning of the receiver enclosure allows the headset to be used by a wide variety of users having different ear shapes and sizes, while providing a stable, comfortable fit and ensuring good acoustic performance. In one embodiment the receiver enclosure is slidably coupled to a ball tube having a ball that rests in a socket of the headset enclosure. The receiver enclosure can telescope along the length of the ball tube and can rotate about an axis of the tube. The ball can be rotated in the socket to position the receiver enclosure at any of a variety of angles relative to the headset enclosure. A voice transmitter is also coupled to the headset enclosure so as to allow adjustment of length, angular position, and rotation.
摘要翻译： 通信耳机包括头戴式耳机外壳和通过各种装置耦合到其的接收器外壳，允许接收器外壳相对于头戴式耳机外壳以各种角度，旋转和距离的任何一种移位。 接收机外壳的适应性定位允许耳机由具有不同耳朵形状和尺寸的各种用户使用，同时提供稳定，舒适的配合并确保良好的声学性能。 在一个实施例中，接收器外壳可滑动地联接到球管上，该球管具有搁置在耳机外壳的插座中的球。 接收器外壳可以沿着球管的长度望远镜并且可以围绕管的轴线旋转。 球可以在插座中旋转以将接收器外壳以相对于耳机外壳的各种角度定位。 语音发射器还耦合到耳机外壳，以便允许调节长度，角度位置和旋转。
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公开(公告)号：US07092837B1
公开(公告)日：2006-08-15
申请号：US10663469
申请日：2003-09-15
申请人： Kenneth J. Lanier , Roger W. Blethen , H. Neil Kelly , Michael G. Davis , Jeffrey H. Perkins , Tommie Berry , Phillip Burlison , Mark Deome , Christopher J. Hannaford , Edward J. Terrenzi , David Menis , David W. Curry , Eric Rosenfeld
发明人： Kenneth J. Lanier , Roger W. Blethen , H. Neil Kelly , Michael G. Davis , Jeffrey H. Perkins , Tommie Berry , Phillip Burlison , Mark Deome , Christopher J. Hannaford , Edward J. Terrenzi , David Menis , David W. Curry , Eric Rosenfeld
IPC分类号： G06F1/06
CPC分类号： G01R31/31903 , G11C29/56 , G11C2029/5602
摘要： An electronic tester with digital, and analog, and memory test circuitry on a single platform. A test head is coupled to a device under test. The device under test can be a system-on-a-chip integrated circuit, a mixed signal integrated circuit, a digital integrated circuit, or an analog integrated circuit. Digital test circuitry applies digital test signals to the device under test coupled to the test head and receives digital outputs from the device under test in response to the digital test signals. Analog test circuitry applies analog test signals to the device under test coupled to the test head and receives analog outputs from the device under test in response to the analog test signals. Memory test circuitry applies memory test patterns to the device under test coupled to the test head and receives memory outputs from the device under test in response to the memory test patterns. A tester computer supervises the application of digital, analog, and memory test signals from the digital, analog, and memory test circuitry to the device under test such that signals applied to the device under test can be solely digital test signals, solely analog test signals, solely memory test signals, or mixed digital, analog, and memory test signals. The test head, the digital test circuitry, the analog test circuitry, the memory test circuitry, and the computer are operable as a single platform.
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公开(公告)号：US06449741B1
公开(公告)日：2002-09-10
申请号：US09183038
申请日：1998-10-30
申请人： Donald V. Organ , Kenneth J. Lanier , Roger W. Blethen , H. Neil Kelly , Michael G. Davis , Jeffrey H. Perkins , Tommie Berry , Phillip Burlison , Mark Deome , Christopher J. Hannaford , Edward J. Terrenzi , David Menis , David W. Curry , Eric Rosenfeld
发明人： Donald V. Organ , Kenneth J. Lanier , Roger W. Blethen , H. Neil Kelly , Michael G. Davis , Jeffrey H. Perkins , Tommie Berry , Phillip Burlison , Mark Deome , Christopher J. Hannaford , Edward J. Terrenzi , David Menis , David W. Curry , Eric Rosenfeld
IPC分类号： H02H305
CPC分类号： G01R1/025 , G01R31/2834 , G01R31/319
摘要： An electronic tester with digital, and analog, and memory test circuitry on a single platform. A test head is coupled to a device under test. The device under test can be a system-on-a-chip integrated circuit, a mixed signal integrated circuit, a digital integrated circuit, or an analog integrated circuit. Digital test circuitry applies digital test signals to the device under test coupled to the test head and receives digital outputs from the device under test in response to the digital test signals. Analog test circuitry applies analog test signals to the device under test coupled to the test head and receives analog outputs from the device under test in response to the analog test signals. Memory test circuitry applies memory test patterns to the device under test coupled to the test head and receives memory outputs from the device under test in response to the memory test patterns. A tester computer supervises the application of digital, analog, and memory test signals from the digital, analog, and memory test circuitry to the device under test such that signals applied to the device under test can be solely digital test signals, solely analog test signals, solely memory test signals, or mixed digital, analog, and memory test signals. The test head, the digital test circuitry, the analog test circuitry, the memory test circuitry, and the computer are operable as a single platform.
摘要翻译： 一个电子测试仪，在单个平台上具有数字，模拟和内存测试电路。 测试头耦合到被测设备。 被测器件可以是片上系统集成电路，混合信号集成电路，数字集成电路或模拟集成电路。 数字测试电路将数字测试信号应用于与测试头相连的被测器件，并响应于数字测试信号接收来自被测器件的数字输出。 模拟测试电路将模拟测试信号应用于与测试头耦合的待测器件，并根据模拟测试信号接收来自被测器件的模拟输出。 存储器测试电路将内存测试模式应用到与测试头耦合的待测器件，并响应于存储器测试模式接收来自被测器件的存储器输出。 测试计算机监控从数字，模拟和存储器测试电路到被测器件的数字，模拟和存储器测试信号的应用，使得施加到被测器件的信号可以是单独的数字测试信号，只有模拟测试信号 ，单独记忆测试信号，或混合数字，模拟和存储器测试信号。 测试头，数字测试电路，模拟测试电路，存储器测试电路和计算机可操作为单个平台。
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公开(公告)号：US06675339B1
公开(公告)日：2004-01-06
申请号：US09935453
申请日：2001-08-22
申请人： Kenneth J. Lanier , Roger W. Blethen , H. Neil Kelly , Michael G. Davis , Jeffrey H. Perkins , Tommie Berry , Phillip Burlison , Mark Deome , Christopher J. Hannaford , Edward J. Terrenzi , David Menis , David W. Curry , Eric Rosenfeld
发明人： Kenneth J. Lanier , Roger W. Blethen , H. Neil Kelly , Michael G. Davis , Jeffrey H. Perkins , Tommie Berry , Phillip Burlison , Mark Deome , Christopher J. Hannaford , Edward J. Terrenzi , David Menis , David W. Curry , Eric Rosenfeld
IPC分类号： G01R3128
CPC分类号： G01R1/025 , G01R31/2834 , G01R31/319
摘要： An electronic tester with digital, and analog, and memory test circuitry on a single platform. A test head is coupled to a device under test. The device under test can be a system-on-a-chip integrated circuit, a mixed signal integrated circuit, a digital integrated circuit, or an analog integrated circuit. Digital test circuitry applies digital test signals to the device under test coupled to the test head and receives digital outputs from the device under test in response to the digital test signals. Analog test circuitry applies analog test signals to the device under test coupled to the test head and receives analog outputs from the device under test in response to the analog test signals. Memory test circuitry applies memory test patters to the device under test coupled to the test head and receives memory outputs from the device under test in response to the memory test patterns. A tester computer supervises the application of digital, analog, and memory test signals from the digital, analog, and memory test circuitry to the device under test such that signals applied to the device under test can be solely digital test signals, solely analog test signals, solely memory test signals, or mixed digital, analog, and memory test signals. The test head, the digital test circuitry, the analog test circuitry, the memory test circuitry, and the computer are operable as a single platform.
摘要翻译： 一个电子测试仪，在单个平台上具有数字，模拟和内存测试电路。 测试头耦合到被测设备。 被测器件可以是片上系统集成电路，混合信号集成电路，数字集成电路或模拟集成电路。 数字测试电路将数字测试信号应用于与测试头相连的被测器件，并响应于数字测试信号接收来自被测器件的数字输出。 模拟测试电路将模拟测试信号应用于与测试头耦合的待测器件，并根据模拟测试信号接收来自被测器件的模拟输出。 存储器测试电路将存储器测试图案应用于被测器件，耦合到测试头，并响应于存储器测试模式接收来自被测器件的存储器输出。 测试计算机监控从数字，模拟和存储器测试电路到被测器件的数字，模拟和存储器测试信号的应用，使得施加到被测器件的信号可以是单独的数字测试信号，只有模拟测试信号 ，单独记忆测试信号，或混合数字，模拟和存储器测试信号。 测试头，数字测试电路，模拟测试电路，存储器测试电路和计算机可操作为单个平台。
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公开(公告)号：US06622541B2
公开(公告)日：2003-09-23
申请号：US09798199
申请日：2001-03-01
IPC分类号： G01M1700
CPC分类号： G01M17/007 , G01M17/0078
摘要： The invention presents a sled device for testing the rollover threshold of a vehicle. The sled has a carriage that is mounted on a track. The carriage can slide upon the track from a first track location. The carriage is configured so that an actual vehicle may be placed on the carriage. When a vehicle is on the carriage, the vehicle is positioned with one side of the vehicle positioned toward the first tract location and the second side of the vehicle positioned toward the second track location. The carriage is propelled from the first tract location to the second track location by an accelerator. As the carriage nears the second track location, a decelerator slows and arrests the movement of the carriage, thereby simulating an impulse potentially sufficient to cause the vehicle to roll.
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公开(公告)号：USD375959S
公开(公告)日：1996-11-26
申请号：US37939
申请日：1995-04-24
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