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    Input output interface controller connecting a synchronous bus to an asynchronous bus and methods for performing operations on the bus
    4.
    发明授权
    Input output interface controller connecting a synchronous bus to an asynchronous bus and methods for performing operations on the bus 失效
    将同步总线连接到异步总线的输入输出接口控制器以及在总线上执行操作的方法

    公开(公告)号：US5199106A

    公开(公告)日：1993-03-30

    申请号：US568530

    申请日：1990-08-15

    申请人： Donall G. Bourke ,  Douglas R. Chisholm ,  Gregory D. Float ,  Richard A. Kelley ,  Roy Y. Liu ,  Carl A. Malmquist ,  John M. Nelson ,  Charles B. Perkins, Jr. ,  Richard L. Place ,  Hartmut R. Schwermer ,  John D. Wilson

    发明人： Donall G. Bourke ,  Douglas R. Chisholm ,  Gregory D. Float ,  Richard A. Kelley ,  Roy Y. Liu ,  Carl A. Malmquist ,  John M. Nelson ,  Charles B. Perkins, Jr. ,  Richard L. Place ,  Hartmut R. Schwermer ,  John D. Wilson

    IPC分类号： G06F13/40

    CPC分类号： G06F13/405

    摘要： In a data processing system, an input output bus unit (IOBU) is connected to one end of an input output interface controller (IOIC) via an asynchronous bus. The other end of the IOIC is connected to a storage controller (SC) and an input output interface unit (IOIU) via a synchronous bus. The SC and IOIU are connected to a memory unit and an instruction processing unit. The asynchronous bus, which is comprised of three sub-buses and a control bus, conducts signals between the IOIC and an IOBU in an asynchronous "handshaking" manner. The synchronous bus, which is comprised of two sub-buses and a control bus, conducts signals between the IOIC and the SC/IOIU in an synchronous manner. The IOIC, interconnected between the synchronous bus and asynchronous bus, functions as a buffer between the faster synchronous bus and the slower asynchronous bus. Various operations are performed between an IOBU and the memory unit via the asynchronous bus, IOIC, synchronous bus, and SC/IOIU, such as a unit operation, a storage operation, and a message acceptance operation.

    摘要翻译： 在数据处理系统中，输入输出总线单元（IOBU）通过异步总线连接到输入输出接口控制器（IOIC）的一端。 IOIC的另一端通过同步总线连接到存储控制器（SC）和输入输出接口单元（IOIU）。 SC和IOIU连接到存储器单元和指令处理单元。 由三个子总线和控制总线组成的异步总线以异步“握手”的方式在IOIC和IOBU之间传输信号。 由两个子总线和控制总线组成的同步总线以同步方式在IOIC和SC / IOIU之间传输信号。 在同步总线和异步总线之间互连的IOIC作为较快的同步总线和较慢的异步总线之间的缓冲器。 通过异步总线，IOIC，同步总线和SC / IOIU在IOBU和存储器单元之间执行各种操作，例如单元操作，存储操作和消息接受操作。

    Arbitration apparatus for determining priority of access to a shared bus on a rotating priority basis
    5.
    发明授权
    Arbitration apparatus for determining priority of access to a shared bus on a rotating priority basis 失效
    用于基于旋转优先级确定对共享总线的访问优先级的仲裁装置

    公开(公告)号：US4760515A

    公开(公告)日：1988-07-26

    申请号：US791647

    申请日：1985-10-28

    申请人： Carl A. Malmquist ,  John D. Wilson

    发明人： Carl A. Malmquist ,  John D. Wilson

    IPC分类号： G06F15/16 ,  G06F13/14 ,  G06F13/30 ,  G06F13/362 ,  G06F13/364 ,  G06F15/177 ,  G06F13/18

    CPC分类号： G06F13/30 ,  G06F13/14 ,  G06F13/364

    摘要： An arbitration apparatus for use within a computer system comprises a plurality of individual arbiters arranged in a particular configuration wherein some individual arbiters are higher in the particular configuration than a specific arbiter and some individual arbiters are lower in the particular configuration than the specific arbiter. Each arbiter has a request terminal for receiving access request signals, requesting access to a shared system bus, and an enable terminal for receiving an enabling signal. The enabling signal is generated and energizes the enable terminal of the specific arbiter if access requests are not received by higher arbiters in the particular configuration relative to the specific arbiter. If an access request signal energizes an arbiter and an enabling signal energizes the arbiter, an access grant signal is developed from the arbiter. If more than one access request signal energizes the arbiter at the same time, a command rotor, connected to the arbiter, determines the priority of access of the request signals to the shared bus in response to the "rotation" of the command rotor. If the access request signal is of a predetermined type, a pre-emptive grant signal may be developed from its arbiter even in the absence of an access request if there are no higher requests and no lower grants. If a refresh request is received by an arbiter when its enabling signal is not received, the refresh request is latched, and a refresh takes place when the enabling signal is finally generated.

    摘要翻译： 在计算机系统内使用的仲裁装置包括以特定配置排列的多个单独仲裁器，其中特定配置中的一些单独仲裁器比特定仲裁器更高，并且某些单独仲裁器在特定配置中比特定仲裁器更低。 每个仲裁器具有用于接收访问请求信号的请求终端，请求访问共享系统总线，以及用于接收使能信号的使能终端。 如果访问请求在特定配置中相对于特定仲裁器没有被较高仲裁者接收，则产生使能信号并且激励特定仲裁器的使能终端。 如果访问请求信号激励仲裁器，并且使能信号激励仲裁器，则从仲裁器开发访问许可信号。 如果多于一个访问请求信号同时给仲裁器通电，则连接到仲裁器的命令转子响应于命令转子的“转动”确定请求信号对共享总线的访问的优先级。 如果访问请求信号是预定类型的，即使没有更高的请求也没有较低的授权，即使没有访问请求，也可以从其仲裁器开发优先授权信号。 如果仲裁器在其接收到使能信号时接收到刷新请求，则刷新请求被锁存，并且当最终产生使能信号时，进行刷新。