公开(公告)号：US08390353B2

公开(公告)日：2013-03-05

申请号：US13332964

申请日：2011-12-21

申请人： Dong Suk Shin ,  Kwang Jin Na

发明人： Dong Suk Shin ,  Kwang Jin Na

IPC分类号： H03K3/017

CPC分类号： H03K5/04

摘要： A duty cycle correction circuit includes a duty correction block configured to generate a first pre-corrected signal and a second pre-corrected signal in response to a duty code and an input signal; a duty-corrected signal generation block configured to generate a duty-corrected signal in response to a first select signal, a second select signal, the first pre-corrected signal and the second pre-corrected signal; and a control block configured to generate the duty code, the first select signal and the second select signal in response to the duty-corrected signal and the input signal.

摘要翻译： 占空比校正电路包括占空比校正块，其被配置为响应于占空比代码和输入信号产生第一预校正信号和第二预校正信号; 配置为响应于第一选择信号，第二选择信号，第一预校正信号和第二预校正信号产生占空比校正信号的占空比校正信号产生块; 以及控制块，被配置为响应于占空比校正信号和输入信号而产生占空比代码，第一选择信号和第二选择信号。

公开(公告)号：US07190203B2

公开(公告)日：2007-03-13

申请号：US11336058

申请日：2006-01-20

申请人： Young Bae Choi ,  Kwang Jin Na

发明人： Young Bae Choi ,  Kwang Jin Na

IPC分类号： H03K3/017

CPC分类号： H03K5/1565 ,  H03K5/151

摘要： A memory device having a duty ratio corrector which can reduce power consumption by blocking current paths between output terminals and a ground terminal by applying input signals for turning off switching devices for generating an auxiliary voltage for correcting a duty ratio at an initial stage, and which can improve an operational speed by changing the auxiliary voltage from a predetermined voltage, not 0V, to a target voltage.

摘要翻译： 一种具有占空比校正器的存储器件，该占空比校正器可以通过施加用于关闭用于产生用于校正初始阶段的占空比的辅助电压的开关器件的输入信号来阻断输出端子与接地端子之间的电流路径来降低功耗，以及哪个 可以通过将辅助电压从预定电压而不是0V改变到目标电压来提高操作速度。

公开(公告)号：US20100172196A1

公开(公告)日：2010-07-08

申请号：US12727185

申请日：2010-03-18

申请人： Kwang Jin Na ,  Young Bae Choi

发明人： Kwang Jin Na ,  Young Bae Choi

IPC分类号： G11C7/00 ,  G11C8/18

CPC分类号： G11C7/1066 ,  G11C7/1051 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4096

摘要： The present invention discloses a circuit for generating a data strobe signal in a DDR memory device and a method therefor which can precisely distinguish preamble and postamble periods of the data strobe signal by generating pulses for generating the data strobe signal only in a data strobe signal input period by using an internal clock signal according to CAS latency under a read command, and generating the data strobe signal by using the pulses, and which can improve reliability of the circuit operation by precisely controlling operation timing with the internal clock signal.

摘要翻译： 本发明公开了一种用于在DDR存储器件中产生数据选通信号的电路及其方法，该电路可以通过仅在数据选通信号输入中产生用于产生数据选通信号的脉冲来精确地区分数据选通信号的前同步码和后同步周期 通过在读取命令下使用根据CAS等待时间的内部时钟信号，并且通过使用脉冲产生数据选通信号，并且通过利用内部时钟信号精确控制操作定时，可以提高电路操作的可靠性。

公开(公告)号：US07605624B2

公开(公告)日：2009-10-20

申请号：US11824840

申请日：2007-06-29

申请人： Kwang Jin Na

发明人： Kwang Jin Na

IPC分类号： H03L7/06

CPC分类号： H03L7/07 ,  H03L7/0812

摘要： A delay locked loop (DLL) circuit is disclosed. The DLL circuit includes a first delay locked loop (DLL) configured to receive a plurality of first clock signals, delay each of the first clock signals by a predetermined period of time in response to a first control signal, and generate a plurality of first internal clock signals and a second delay locked loop (DLL) configured to receive the first internal clock signals, delay the first internal clock signals by a predetermined period of time in response to a second control signal, and generate a plurality of second internal clock signals.

摘要翻译： 公开了一种延迟锁定环（DLL）电路。 DLL电路包括被配置为接收多个第一时钟信号的第一延迟锁定环（DLL），响应于第一控制信号将每个第一时钟信号延迟预定的时间段，并且产生多个第一内部 时钟信号和第二延迟锁定环（DLL），被配置为接收第一内部时钟信号，响应于第二控制信号将第一内部时钟信号延迟预定时间段，并产生多个第二内部时钟信号。

公开(公告)号：US20090168548A1

公开(公告)日：2009-07-02

申请号：US12173724

申请日：2008-07-15

申请人： Kwang Jin Na

发明人： Kwang Jin Na

IPC分类号： G11C7/00 ,  G11C8/18

CPC分类号： G11C7/1051 ,  G11C7/1057 ,  G11C7/1066

摘要： A data output circuit in a semiconductor memory apparatus includes a first data driving unit configured to generate a first driving data at a first timing, a first buffering unit configured to generate a first output data by buffering the first driving data, a second data driving unit configured to generate a second driving data at a second timing that is different from the first timing, and a second buffering unit configured to generate a second output data by buffering the second driving data.

摘要翻译： 半导体存储装置中的数据输出电路包括：第一数据驱动单元，被配置为在第一定时产生第一驱动数据;第一缓冲单元，被配置为通过缓冲第一驱动数据产生第一输出数据;第二数据驱动单元 被配置为在与第一定时不同的第二定时产生第二驱动数据，以及第二缓冲单元，被配置为通过缓冲第二驱动数据来生成第二输出数据。

公开(公告)号：US20110148487A1

公开(公告)日：2011-06-23

申请号：US13038604

申请日：2011-03-02

申请人： Kwang Jin Na

发明人： Kwang Jin Na

IPC分类号： H03L7/06

CPC分类号： H03L7/10 ,  H03L7/07 ,  H03L7/0812 ,  H03L7/0814 ,  H03L7/087

摘要： A DLL circuit includes a clock selection control unit configured to generate a clock selection signal on the basis of a phase difference between a reference clock and a feedback clock and, after the clock selection signal is generated, to generate an initialization signal. A delay control unit, when the initialization signal is enabled, transfers an initial voltage to be generated by dividing an external power supply voltage to a delay unit as a control voltage, and controls a delay operation of a delay reference clock to be selected on the basis of the clock selection signal.

摘要翻译： DLL电路包括：时钟选择控制单元，被配置为基于参考时钟和反馈时钟之间的相位差产生时钟选择信号，并且在产生时钟选择信号之后生成初始化信号。 延迟控制单元，当初始化信号被使能时，通过将外部电源电压分配为延迟单元作为控制电压来传送要产生的初始电压，并且控制在所选择的延迟基准时钟的延迟操作 时钟选择信号的基础。

公开(公告)号：US20080042704A1

公开(公告)日：2008-02-21

申请号：US11647904

申请日：2006-12-28

申请人： Kwang Jin Na

发明人： Kwang Jin Na

IPC分类号： H03L7/06

CPC分类号： H03L7/093 ,  H03L7/0814 ,  H03L7/089

摘要： A delayed locked loop (DLL) circuit is provided which includes a delay line for including a plurality of delay elements, and delaying an internal clock signal generated by buffering external clock signals by a first delay period, an internal delay for delaying an output signal of the delay line by a second delay period determined by modeling delay elements contained in a DRAM, and generating a feedback clock signal, a phase detector for generating an enable signal enabled when a phase difference between the feedback clock signal and a reference clock signal is contained in a predetermined period, and outputs the enable signal, a delay-period controller configured to generate, in response to the enable signal, first and second control signals for adjusting a counter output signal corresponding to at least one delay element selected from among the delay elements, a counter for receiving the first and second control signals, and generating a counter output signal corresponding to the at least one delay element, and a decoder for decoding the counter output signal, and generating the decoding signal, wherein the decoding signal indicates an enable state of the at least one delay element and adjusts the first delay period.

摘要翻译： 提供了一种延迟锁定环路（DLL）电路，其包括用于包括多个延迟元件的延迟线，以及延迟通过将外部时钟信号缓冲第一延迟周期产生的内部时钟信号，用于延迟输出信号的输出信号 所述延迟线通过由包含在DRAM中的延迟元件建模确定并且产生反馈时钟信号所确定的第二延迟周期;相位检测器，用于在反馈时钟信号和参考时钟信号之间的相位差被包含时产生使能信号使能 在预定时段内输出使能信号，延迟周期控制器被配置为响应于使能信号产生用于调整与从延迟中选择的至少一个延迟元件相对应的计数器输出信号的第一和第二控制信号 元件，用于接收第一和第二控制信号的计数器，以及产生对应于at1的计数器输出信号 东一延迟元件和解码器，用于解码计数器输出信号，并产生解码信号，其中解码信号指示至少一个延迟元件的使能状态并调整第一延迟周期。

公开(公告)号：US07312647B2

公开(公告)日：2007-12-25

申请号：US11623927

申请日：2007-01-17

申请人： Young Bae Choi ,  Kwang Jin Na

发明人： Young Bae Choi ,  Kwang Jin Na

IPC分类号： H03K3/017

CPC分类号： H03K5/1565 ,  H03K5/151

摘要： A memory device having a duty ratio corrector which can reduce power consumption by blocking current paths between output terminals and a ground terminal by applying input signals for turning off switching devices for generating an auxiliary voltage for correcting a duty ratio at an initial stage, and which can improve an operational speed by changing the auxiliary voltage from a predetermined voltage, not 0V, to a target voltage.

公开(公告)号：US6157238A

公开(公告)日：2000-12-05

申请号：US104987

申请日：1998-06-26

申请人： Kwang Jin Na ,  Seong Ik Cho

发明人： Kwang Jin Na ,  Seong Ik Cho

IPC分类号： G06F1/10 ,  H03K5/00 ,  H03K5/156 ,  H03K3/00

CPC分类号： H03K5/00006 ,  G06F1/10 ,  H03K5/1565

摘要： A clock system produces a high-speed clock signal based on a low-speed clock signal inputted from the outside through the use of a frequency amplifier therein in order to thereby reduce power consumption at a clock buffer. In order to perform the above process, the clock system is composed of an external clock source for producing a clock signal having a frequency of f, a plurality of Rambus DRAMs and a controller, which are synchronized by the clock signal derived from the external clock source. By using the clock system, it is possible to reduce power consumption at the clock buffer and to decrease occurrence of a high frequency noise at a clock pin, and thus, a high qualified system design is also accomplished.

摘要翻译： 时钟系统基于通过使用其中的频率放大器从外部输入的低速时钟信号产生高速时钟信号，从而降低时钟缓冲器的功耗。 为了执行上述处理，时钟系统由用于产生具有频率f的时钟信号的外部时钟源，多个Rambus DRAM和控制器组成，其由来自外部时钟的时钟信号同步 资源。 通过使用时钟系统，可以降低时钟缓冲器的功耗并减少时钟引脚上的高频噪声的发生，从而也可以实现高质量的系统设计。

公开(公告)号：US08390350B2

公开(公告)日：2013-03-05

申请号：US12845416

申请日：2010-07-28

申请人： Kwang Jin Na

发明人： Kwang Jin Na

IPC分类号： H03L7/06

CPC分类号： H03L7/0816

摘要： A clock signal delay circuit includes a variable delay unit, a delay unit, a phase detection block, a control clock output block, and a delay control unit. The variable delay unit controls a delay amount of a reference clock signal based on a delay control signal and provides a delayed clock signal based thereon. The delay unit delays the delayed clock signal and provides a feedback clock signal based thereon. The phase detection block detects a phase difference between the feedback clock signal and the reference clock signal and provides a detected phase difference based thereon. The control clock output block provides a control clock signal based on the detected phase difference. The delay control unit generates the delay control signal based on the detected phase difference and in response to the control clock signal.

摘要翻译： 时钟信号延迟电路包括可变延迟单元，延迟单元，相位检测块，控制时钟输出块和延迟控制单元。 可变延迟单元基于延迟控制信号控制参考时钟信号的延迟量，并且基于延迟控制信号提供延迟的时钟信号。 延迟单元延迟延迟的时钟信号并且基于此提供反馈时钟信号。 相位检测块检测反馈时钟信号和参考时钟信号之间的相位差，并基于此检测相位差。 控制时钟输出块基于检测到的相位差提供控制时钟信号。 延迟控制单元根据所检测的相位差和响应于控制时钟信号产生延迟控制信号。