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    FREQUENCY DETECTOR AND OPERATING METHOD THEREOF
    1.
    发明公开
    FREQUENCY DETECTOR AND OPERATING METHOD THEREOF 审中-公开

    公开(公告)号：US20240275390A1

    公开(公告)日：2024-08-15

    申请号：US18361059

    申请日：2023-07-28

    申请人： Samsung Electronics Co., Ltd.

    发明人： Jahoon JIN ,  Sangho KIM ,  Kyunghwan MIN ,  Soomin LEE ,  Sodam JU

    IPC分类号： H03L7/091 ,  H03L7/081

    CPC分类号： H03L7/091 ,  H03L7/0816 ,  H03L2207/06

    摘要： Disclosed is a frequency detector. The frequency detector includes a first flip-flop sampling a clock signal based on a data signal to generate a first signal, a second flip-flop sampling a delayed-phase component of the clock signal based on the data signal or sampling the clock signal based on a delayed-phase component of the data signal to generate a second signal, a third flip-flop generating a third signal representing a polarity of a frequency difference between a data rate of the data signal and a frequency of the clock signal based on the first signal and the second signal, and a delay cell generating the delayed-phase component of the clock signal or the delayed-phase component of the data signal. The delayed-phase component has a delay amount set to a value smaller than about 0.25 UI.

    CLOCK GENERATING CIRCUIT AND SEMICONDUCTOR APPARATUS USING THE SAME
    3.
    发明公开
    CLOCK GENERATING CIRCUIT AND SEMICONDUCTOR APPARATUS USING THE SAME 审中-公开

    公开(公告)号：US20240072810A1

    公开(公告)日：2024-02-29

    申请号：US18084956

    申请日：2022-12-20

    申请人： SK hynix Inc.

    发明人： Gyu Tae PARK ,  Young Jae AN

    IPC分类号： H03L7/081 ,  H03K5/135

    CPC分类号： H03L7/0816 ,  H03K5/135

    摘要： A clock generating circuit includes a first division circuit and a second division circuit. The first division circuit is configured to generate a first group of internal clock signals by dividing a clock signal. The second division circuit is configured to generate a second group of internal clock signals by dividing a delayed clock signal, the delayed clock signal generated by an internal circuit delaying the clock signal. An operation timing of the second division circuit can be adjusted based on one of the first group of internal clock signals generated by the first division circuit.

    Asynchronous ASIC
    5.
    发明授权
    Asynchronous ASIC 有权

    公开(公告)号：US11747856B2

    公开(公告)日：2023-09-05

    申请号：US18175466

    申请日：2023-02-27

    申请人： Magic Leap, Inc.

    发明人： Niv Margalit ,  Eyal Sela

    IPC分类号： G06F1/06 ,  G06F1/10 ,  G06F1/12 ,  H03L7/081

    CPC分类号： G06F1/12 ,  G06F1/06 ,  G06F1/10 ,  H03L7/0816

    摘要： An electronic device is disclosed. The electronic device comprises a first clock configured to operate at a frequency. First circuitry of the electronic device is configured to synchronize with the first clock. Second circuitry is configured to determine a second clock based on the first clock. The second clock is configured to operate at the frequency of the first clock, and is further configured to operate with a phase shift with respect to the first clock. Third circuitry is configured to synchronize with the second clock.

    Memory package, semiconductor device, and storage device
    6.
    发明授权
    Memory package, semiconductor device, and storage device 有权

    公开(公告)号：US11736098B2

    公开(公告)日：2023-08-22

    申请号：US17866517

    申请日：2022-07-17

    申请人： Samsung Electronics Co., Ltd.

    发明人： Tongsung Kim ,  Youngmin Jo ,  Chiweon Yoon ,  Byungkwan Chun ,  Byunghoon Jeong

    IPC分类号： H03K5/14 ,  H03L7/081 ,  H03K5/135 ,  H03K5/00

    CPC分类号： H03K5/14 ,  H03K5/135 ,  H03L7/0816 ,  H03K2005/00247

    摘要： A memory package includes a plurality of memory chips, and an interface chip relaying communications between a controller and the plurality of memory chips and receiving a plurality of signals from the plurality of memory chips. The interface chip includes receivers outputting a data signal and a raw clock signal based on the plurality of signals, a delay circuit outputting a delay clock signal by applying an offset delay corresponding to ½ of one unit interval of the data signal and an additional delay to the raw clock signal, and a sampler sampling the data signal in synchronization with a clock signal. The delay circuit outputs the clock signal generated by removing the offset delay from the delay clock signal when the delay clock signal and the data signal have a phase difference corresponding to one unit interval of the data signal.

    Increased phase interpolator linearity in phase-locked loop
    8.
    发明授权
    Increased phase interpolator linearity in phase-locked loop 有权

    公开(公告)号：US11646742B1

    公开(公告)日：2023-05-09

    申请号：US17526753

    申请日：2021-11-15

    申请人： NVIDIA Corporation

    发明人： Yi-Chieh Huang ,  Ying Wei ,  Bo-Yu Chen

    IPC分类号： H03L7/087 ,  H03L7/099 ,  H03K19/173 ,  H03L7/083 ,  H03L7/081

    CPC分类号： H03L7/0998 ,  H03K19/1737 ,  H03L7/083 ,  H03L7/0816

    摘要： A phase-locked loop (PLL) device includes a first phase detector to receive an in-phase reference clock and an in-phase feedback clock, the first phase detector to output a first phase error; a second phase detector to receive a quadrature reference clock and a quadrature feedback clock, the second phase detector to output a second phase error; a proportional path component to generate first current pulses from the first phase error and second current pulses from the second phase error; an integrator circuit coupled to the proportional path component, the integrator circuit to sum, within a current output signal, the first current pulses and the second current pulses; a ring oscillator to be driven by the current output signal; and a pair of phase interpolators coupled to an output of the ring oscillator, the pair of phase interpolators to respectively generate the in-phase feedback clock and the quadrature feedback clock.