公开(公告)号：US07888237B2

公开(公告)日：2011-02-15

申请号：US12265165

申请日：2008-11-05

申请人： Dong-Han Kim ,  Kyoung-Sei Choi ,  Chul-woo Kim

发明人： Dong-Han Kim ,  Kyoung-Sei Choi ,  Chul-woo Kim

IPC分类号： H01L21/00

CPC分类号： H01L21/67092 ,  B28D5/0011 ,  H01L21/78

摘要： A method of cutting a semiconductor wafer includes preparing a semiconductor wafer including a scribe region and a chip region, forming a groove in the scribe region, loading the semiconductor wafer with the groove formed therein in a chamber, and cutting the semiconductor wafer into a plurality of chips through increasing a pressure of the chamber by a first pressure change rate, and then reducing the pressure of the chamber by a second pressure change rate.

摘要翻译： 切割半导体晶片的方法包括制备包括划线区域和芯片区域的半导体晶片，在刻划区域形成沟槽，将其中形成有槽的半导体晶片装载在室中，并将半导体晶片切割成多个 通过增加室的压力达到第一压力变化率，然后将室的压力降低第二压力变化率。

公开(公告)号：US20090117710A1

公开(公告)日：2009-05-07

申请号：US12265165

申请日：2008-11-05

申请人： Dong-Han KIM ,  Kyoung-Sei Choi ,  Chul-woo Kim

发明人： Dong-Han KIM ,  Kyoung-Sei Choi ,  Chul-woo Kim

IPC分类号： H01L21/00

CPC分类号： H01L21/67092 ,  B28D5/0011 ,  H01L21/78

摘要： A method of cutting a semiconductor wafer includes preparing a semiconductor wafer including a scribe region and a chip region, forming a groove in the scribe region, loading the semiconductor wafer with the groove formed therein in a chamber, and cutting the semiconductor wafer into a plurality of chips through increasing a pressure of the chamber by a first pressure change rate, and then reducing the pressure of the chamber by a second pressure change rate.

摘要翻译： 切割半导体晶片的方法包括制备包括划线区域和芯片区域的半导体晶片，在刻划区域形成沟槽，将其中形成有槽的半导体晶片装载在室中，并将半导体晶片切割成多个 通过增加室的压力达到第一压力变化率，然后将室的压力降低第二压力变化率。

公开(公告)号：US20100244914A1

公开(公告)日：2010-09-30

申请号：US12691023

申请日：2010-01-21

申请人： Chul-woo Kim ,  Woo-seok Kim ,  Min-young Song ,  Jae-jin Park ,  Ji-hyun Kim ,  Young-ho Kwak

发明人： Chul-woo Kim ,  Woo-seok Kim ,  Min-young Song ,  Jae-jin Park ,  Ji-hyun Kim ,  Young-ho Kwak

IPC分类号： H03L7/06

CPC分类号： H03L7/23 ,  H03L7/085 ,  H03L7/0991 ,  H03L7/1075 ,  H03L2207/06 ,  H03L2207/50

摘要： A clock generator includes a controller, a digital phase locked loop (PLL) circuit, a charge pump phase locked loop (PLL) circuit and a divider. The controller generates a division factor and a first internal clock signal in response to a low-frequency reference clock signal and a multiplication factor. The digital PLL circuit generates a second internal clock signal in response to the reference clock signal, the division factor and the first internal clock signal. The charge pump PLL circuit generates a plurality of third internal clock signals by using the second internal clock signal. The divider generates a high-frequency clock signal in response to a phase selection signal, the division factor and the third internal clock signals.

摘要翻译： 时钟发生器包括控制器，数字锁相环（PLL）电路，电荷泵锁相环（PLL）电路和分频器。 响应于低频参考时钟信号和乘法因子，控制器产生除法系数和第一内部时钟信号。 数字PLL电路响应于参考时钟信号，分频因子和第一内部时钟信号产生第二内部时钟信号。 电荷泵PLL电路通过使用第二内部时钟信号产生多个第三内部时钟信号。 分频器响应于相位选择信号，分频因子和第三内部时钟信号产生高频时钟信号。

公开(公告)号：US08149030B2

公开(公告)日：2012-04-03

申请号：US12691023

申请日：2010-01-21

申请人： Chul-woo Kim ,  Woo-seok Kim ,  Min-young Song ,  Jae-jin Park ,  Ji-hyun Kim ,  Young-ho Kwak

发明人： Chul-woo Kim ,  Woo-seok Kim ,  Min-young Song ,  Jae-jin Park ,  Ji-hyun Kim ,  Young-ho Kwak

IPC分类号： H03L7/06

CPC分类号： H03L7/23 ,  H03L7/085 ,  H03L7/0991 ,  H03L7/1075 ,  H03L2207/06 ,  H03L2207/50

摘要： A clock generator includes a controller, a digital phase locked loop (PLL) circuit, a charge pump phase locked loop (PLL) circuit and a divider. The controller generates a division factor and a first internal clock signal in response to a low-frequency reference clock signal and a multiplication factor. The digital PLL circuit generates a second internal clock signal in response to the reference clock signal, the division factor and the first internal clock signal. The charge pump PLL circuit generates a plurality of third internal clock signals by using the second internal clock signal. The divider generates a high-frequency clock signal in response to a phase selection signal, the division factor and the third internal clock signals.

摘要翻译： 时钟发生器包括控制器，数字锁相环（PLL）电路，电荷泵锁相环（PLL）电路和分频器。 响应于低频参考时钟信号和乘法因子，控制器产生除法系数和第一内部时钟信号。 数字PLL电路响应于参考时钟信号，分频因子和第一内部时钟信号产生第二内部时钟信号。 电荷泵PLL电路通过使用第二内部时钟信号产生多个第三内部时钟信号。 分频器响应于相位选择信号，分频因子和第三内部时钟信号产生高频时钟信号。