公开(公告)号：US20050218788A1

公开(公告)日：2005-10-06

申请号：US11085262

申请日：2005-03-22

Applicant: Dong-Su Jang ,  Jae-Hoon Lee

Inventor： Dong-Su Jang ,  Jae-Hoon Lee

IPC: H01J1/30 ,  H01J19/02 ,  H01J29/46 ,  H01J29/84

CPC classification number: H01J29/84 ,  H01J29/467

Abstract: An electron emission display includes: a rear plate including an electron emission device; a front plate spaced from the rear plate and including a fluorescent layer adapted to emit light in response to electrons emitted by the electron emission device colliding with the fluorescent layer; and a grid electrode arranged in a space between the rear and front plates and having a grid substrate including an aperture through which electrons emitted by the electron emission device pass and a film of a photo absorbing material arranged on a surface of the grid substrate. With this configuration, light from a fluorescent layer or secondary electrons, which travel towards a rear plate while the electron emission display operates, are absorbed in the blackened film to prevent other fluorescent layers from emitting light, thereby improving brightness and color purity of the electron emission display.

Abstract translation: 电子发射显示器包括：包括电子发射装置的后板; 与所述后板间隔开的前板，并且包括适于响应于与所述荧光层相撞的所述电子发射器件发射的电子而发光的荧光层; 以及布置在后板和前板之间的空间中的栅格电极，并且具有栅格基板，该栅格基板包括通过电子发射器件发射的电子的孔和布置在栅格衬底的表面上的光吸收材料的膜。 利用这种构造，在电子发射显示器操作时从背面板行进的来自荧光层的光或二次电子被吸收在黑色的膜中以防止其它荧光层发光，从而提高电子的亮度和色纯度 发射显示。

公开(公告)号：US07852703B2

公开(公告)日：2010-12-14

申请号：US12177716

申请日：2008-07-22

Applicant: Dong-Su Jang ,  In-Chul Jeong

Inventor： Dong-Su Jang ,  In-Chul Jeong

IPC: G11C8/00

CPC classification number: G11C8/08 ,  G11C5/025 ,  G11C5/063 ,  G11C8/14

Abstract: A semiconductor memory device and a layout structure of sub-word line control signal generators. The sub-word line control signal generators are configured to supply a sub-word line control signal of a predefined voltage level to a sub-word line driver to enable a sub-word line of a memory cell array. At least two sub-word line control signal generators are disposed, respectively, at edge areas of the memory cell array, to directly supply the sub-word line control signal to one selected sub-word line driver, thereby reducing the power consumption, including for example, VPP voltage. Embodiments of the present invention also reduce the number of VPP power lines, thereby lessening a noise disturbance.

Abstract translation: 半导体存储器件和子字线控制信号发生器的布局结构。 子字线控制信号发生器被配置为向子字线驱动器提供预定电压电平的子字线控制信号，以使能存储单元阵列的子字线。 至少两个子字线控制信号发生器分别设置在存储单元阵列的边缘区域，以便将子字线控制信号直接提供给一个所选择的子字线驱动器，从而降低功耗，包括 例如VPP电压。 本发明的实施例还减少VPP电力线的数量，从而减少噪声干扰。

公开(公告)号：US08203904B2

公开(公告)日：2012-06-19

申请号：US12962951

申请日：2010-12-08

Applicant: Dong-Su Jang ,  In-Chul Jeong

Inventor： Dong-Su Jang ,  In-Chul Jeong

IPC: G11C8/00

CPC classification number: G11C8/08 ,  G11C5/025 ,  G11C5/063 ,  G11C8/14

Abstract: A semiconductor memory device and a layout structure of sub-word line control signal generators. The sub-word line control signal generators are configured to supply a sub-word line control signal of a predefined voltage level to a sub-word line driver to enable a sub-word line of a memory cell array. At least two sub-word line control signal generators are disposed, respectively, at edge areas of the memory cell array, to directly supply the sub-word line control signal to one selected sub-word line driver, thereby reducing the power consumption, including for example, VPP voltage. Embodiments of the present invention also reduce the number of VPP power lines, thereby lessening a noise disturbance.

Abstract translation: 半导体存储器件和子字线控制信号发生器的布局结构。 子字线控制信号发生器被配置为向子字线驱动器提供预定电压电平的子字线控制信号，以使能存储单元阵列的子字线。 至少两个子字线控制信号发生器分别设置在存储单元阵列的边缘区域，以便将子字线控制信号直接提供给一个所选择的子字线驱动器，从而降低功耗，包括 例如VPP电压。 本发明的实施例还减少VPP电力线的数量，从而减少噪声干扰。

公开(公告)号：US08243535B2

公开(公告)日：2012-08-14

申请号：US12731465

申请日：2010-03-25

Applicant: Dong-Su Jang ,  Yong-Ho Cho

Inventor： Dong-Su Jang ,  Yong-Ho Cho

IPC: G11C7/00

CPC classification number: G11C11/4091 ,  G11C7/08 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076

Abstract: A semiconductor memory device comprises a memory cell configured to output data to a pair of bitlines, a variable delay circuit configured to receive a sense amplifier enable signal, adjust a delay of the sense amplifier enable signal by changing a slope of a delay based on a variable external power supply voltage, and output a delayed sense amplifier enable signal, and a bitline sense amplifier configured to amplify a voltage difference between the pair of bitlines in response to the delayed sense amplifier enable signal and output the amplified voltage difference to a pair of input/output lines.

Abstract translation: 一种半导体存储器件包括被配置为将数据输出到一对位线的存储单元，可变延迟电路，被配置为接收读出放大器使能信号，通过改变基于a的延迟的斜率来调整读出放大器使能信号的延迟 可变外部电源电压，并输出延迟读出放大器使能信号;以及位线读出放大器，被配置为响应延迟的读出放大器使能信号放大该对位线之间的电压差，并将放大的电压差输出到一对 输入/输出线。