公开(公告)号：US4242720A

公开(公告)日：1980-12-30

申请号：US831895

申请日：1977-09-09

Applicant: Donn Moore

Inventor： Donn Moore

IPC: H01R12/51 ,  H05K1/00 ,  H05K1/02 ,  H05K1/16 ,  H05K3/22 ,  H05K1/04

CPC classification number: H05K1/0246 ,  H05K3/222 ,  H05K1/0218 ,  H05K1/0287 ,  H05K1/167 ,  H05K2201/0715 ,  H05K2201/10174 ,  H05K2201/10287 ,  H05K2201/10303 ,  H05K2201/10333 ,  H05K2201/10689

Abstract: A logic card for interconnection of integrated circuits comprises a laminate for supporting integrated circuit devices. The laminate includes a relatively highly conductive layer. A selected plurality of holes are formed through the laminate in selected patterns at each of a plurality of stations on the laminate. A conductor is disposed in each of the holes. The conductors comprise, in each pattern, first and second groups of conductors. The conductors in each first group have one end effectively exposed on one side of the laminate and the conductors in each second group in each pattern have their opposite ends effectively exposed on opposite sides of the laminate, thus adapting the conductors for connection thereto of either or both of a lead from an integrated circuit and a conductor wire. Coupling means are located internally of the laminate for coupling the conductive layer to the in-hole conductors of the first group in each pattern and defining between the conductive layer and each said conductor a transmission line termination device.

Abstract translation: 用于集成电路互连的逻辑卡包括用于支撑集成电路器件的叠层。 层压体包括相对高导电性的层。 在层压板上的多个工位中的每一个台阶上，选定的多个孔以选定的图案形成穿过层叠体。 导体设置在每个孔中。 导体在每个图案中包括第一组和第二组导体。 每个第一组中的导体具有有效地暴露在层压体的一侧上的导体，并且每个图案中的每个第二组中的导体的相对端部有效地暴露在层叠体的相对侧上，从而使导体与其中的一个或 来自集成电路的导线和导线。 耦合装置位于层压板的内部，用于将导电层连接到每个图案中的第一组的空穴导体，并且在导电层和每个所述导体之间限定传输线终端装置。