公开(公告)号：US20070047367A1

公开(公告)日：2007-03-01

申请号：US11506878

申请日：2006-08-21

申请人： Doo-Young Kim ,  Soon-Seob Lee ,  Chul-Soo Kim

发明人： Doo-Young Kim ,  Soon-Seob Lee ,  Chul-Soo Kim

IPC分类号： G11C8/00

CPC分类号： G11C8/10

摘要： Semiconductor memory devices, block select decoding circuits and a method of activating a word line are provided. An example semiconductor memory device may include a plurality of memory banks. Each of the plurality of memory banks may include memory blocks which may be arranged in different addressable orders. If two edge memory blocks are activated in a given one of the plurality of memory banks, a non-edge memory block may be concurrently activated in at least one of remaining memory banks other than the given one memory bank. Accordingly, a number of concurrently activated memory blocks, a voltage required to enable a word line and noise may be reduced. The example semiconductor device may include the example block select decoding circuit, and likewise may perform the example method of activating a word line with an activation of a reduced number of memory blocks.

摘要翻译： 提供半导体存储器件，块选择解码电路和激活字线的方法。 示例性半导体存储器件可以包括多个存储体。 多个存储体中的每一个可以包括可以以不同的可寻址顺序排列的存储块。 如果在多个存储体中的给定的一个存储体中激活了两个边缘存储器块，则非边缘存储器块可以在除给定的一个存储体之外的剩余存储体的至少一个中同时激活。 因此，可以减少多个同时激活的存储块，使得字线和噪声所需的电压。 示例性半导体器件可以包括示例块选择解码电路，并且同样可以执行用减少数量的存储器块的激活来激活字线的示例方法。

公开(公告)号：US07471589B2

公开(公告)日：2008-12-30

申请号：US11506878

申请日：2006-08-21

申请人： Doo-Young Kim ,  Soon-Seob Lee ,  Chul-Soo Kim

发明人： Doo-Young Kim ,  Soon-Seob Lee ,  Chul-Soo Kim

IPC分类号： G11C7/00

CPC分类号： G11C8/10

摘要： Semiconductor memory devices, block select decoding circuits and a method of activating a word line are provided. An example semiconductor memory device may include a plurality of memory banks. Each of the plurality of memory banks may include memory blocks which may be arranged in different addressable orders. If two edge memory blocks are activated in a given one of the plurality of memory banks, a non-edge memory block may be concurrently activated in at least one of remaining memory banks other than the given one memory bank. Accordingly, a number of concurrently activated memory blocks, a voltage required to enable a word line and noise may be reduced. The example semiconductor device may include the example block select decoding circuit, and likewise may perform the example method of activating a word line with an activation of a reduced number of memory blocks.

摘要翻译： 提供半导体存储器件，块选择解码电路和激活字线的方法。 示例性半导体存储器件可以包括多个存储体。 多个存储体中的每一个可以包括可以以不同的可寻址顺序排列的存储块。 如果在多个存储体中的给定的一个存储体中激活了两个边缘存储器块，则非边缘存储器块可以在除给定的一个存储体之外的剩余存储体的至少一个中同时激活。 因此，可以减少多个同时激活的存储块，使得字线和噪声所需的电压。 示例性半导体器件可以包括示例块选择解码电路，并且同样可以执行用减少数量的存储器块的激活来激活字线的示例方法。

公开(公告)号：US20070280018A1

公开(公告)日：2007-12-06

申请号：US11523052

申请日：2006-09-19

申请人： Soon-Seob Lee ,  Dae-Joon Kim ,  Dong-Ho Hyeon

发明人： Soon-Seob Lee ,  Dae-Joon Kim ,  Dong-Ho Hyeon

IPC分类号： G11C7/00 ,  G11C8/00

CPC分类号： G11C7/12

摘要： A semiconductor memory device, a local precharge circuit and a method thereof are provided. The example semiconductor memory device may include a local input/output line connected to a bit line coupled with a memory cell, through a column selection transistor, the local input/output line providing a transmission path on which to transmit a data signal through the bit line to a local sense amplifier and a local precharge circuit configured to adjust a precharge voltage level of the local input/output line based on a status of an active mode and a status of a column selection signal. The example local precharge circuit may be included within the example semiconductor memory device. The example semiconductor memory device including the example local precharge circuit may be capable of adjusting a precharge voltage level of the local input/output line based on a status of an active mode and a status of a column selection signal, the active mode referring to a period where a word line is enabled.

摘要翻译： 提供半导体存储器件，局部预充电电路及其方法。 示例性半导体存储器件可以包括通过列选择晶体管连接到与存储器单元耦合的位线的本地输入/输出线，该本地输入/输出线提供在其上通过位发送数据信号的传输路径 线路连接到本地感测放大器和局部预充电电路，其被配置为基于活动模式的状态和列选择信号的状态来调整本地输入/输出线的预充电电压电平。 示例性局部预充电电路可以包括在示例半导体存储器件内。 包括示例性局部预充电电路的示例半导体存储器件可以能够基于活动模式的状态和列选择信号的状态来调整本地输入/输出线的预充电电压电平，活动模式参考 启用字线的时间段。

公开(公告)号：US07477558B2

公开(公告)日：2009-01-13

申请号：US11523052

申请日：2006-09-19

申请人： Soon-Seob Lee ,  Dae-Joon Kim ,  Dong-Ho Hyeon

发明人： Soon-Seob Lee ,  Dae-Joon Kim ,  Dong-Ho Hyeon

IPC分类号： G11C7/00

CPC分类号： G11C7/12

摘要： A semiconductor memory device, a local precharge circuit and a method thereof are provided. The example semiconductor memory device may include a local input/output line connected to a bit line coupled with a memory cell, through a column selection transistor, the local input/output line providing a transmission path on which to transmit a data signal through the bit line to a local sense amplifier and a local precharge circuit configured to adjust a precharge voltage level of the local input/output line based on a status of an active mode and a status of a column selection signal. The active mode may be a period where a word line is enabled. The example local precharge circuit may be included within the example semiconductor memory device.

摘要翻译： 提供半导体存储器件，局部预充电电路及其方法。 示例性半导体存储器件可以包括通过列选择晶体管连接到与存储器单元耦合的位线的本地输入/输出线，该本地输入/输出线提供在其上通过位发送数据信号的传输路径 线路连接到本地感测放大器和局部预充电电路，其被配置为基于活动模式的状态和列选择信号的状态来调整本地输入/输出线的预充电电压电平。 活动模式可以是启用字线的时段。 示例性局部预充电电路可以包括在示例半导体存储器件内。

公开(公告)号：US20080084233A1

公开(公告)日：2008-04-10

申请号：US11755836

申请日：2007-05-31

申请人： Soon-Seob Lee

发明人： Soon-Seob Lee

IPC分类号： H03L7/06

CPC分类号： H03L7/095 ,  H03L7/089

摘要： A frequency regulator including a phase frequency detector and a lock detection unit. The phase frequency detector receives a reference signal and a feedback signal, compares a phase of the reference signal and a phase of the feedback signal, and outputs a first control signal and a second control signal to regulate phase and frequency of the feedback signal. The lock detection unit generates a phase lock signal in a case of keeping that a time difference between the first control signal and the second control signal is smaller than a reference time during an interval time period of at least a half period of the reference signal.

摘要翻译： 一种频率调节器，包括相位频率检测器和锁定检测单元。 相位频率检测器接收参考信号和反馈信号，比较参考信号的相位和反馈信号的相位，并输出第一控制信号和第二控制信号以调节反馈信号的相位和频率。 在基准信号的至少半周期的间隔时间段内，在保持第一控制信号和第二控制信号之间的时间差小于基准时间的情况下，锁定检测单元产生锁相信号。

公开(公告)号：US08036056B2

公开(公告)日：2011-10-11

申请号：US12232719

申请日：2008-09-23

申请人： Soon-Seob Lee

发明人： Soon-Seob Lee

IPC分类号： G11C7/00

CPC分类号： G11C7/1048 ,  G11C7/1006 ,  G11C11/4076 ,  G11C11/4096

摘要： A semiconductor memory device includes a memory cell array and an input/output path circuit. The input/output path circuit performs an input/output line pre-charge operation at a write end time point and outputs data stored in the memory cell array when the semiconductor memory device is operated in a read mode.

摘要翻译： 半导体存储器件包括存储单元阵列和输入/输出路径电路。 输入/输出路径电路在写入结束时间点执行输入/输出线预充电操作，并且当半导体存储器件以读取模式操作时，输出存储在存储单元阵列中的数据。

公开(公告)号：US20090086553A1

公开(公告)日：2009-04-02

申请号：US12232719

申请日：2008-09-23

申请人： Soon-Seob Lee

发明人： Soon-Seob Lee

IPC分类号： G11C7/00 ,  G11C8/08

CPC分类号： G11C7/1048 ,  G11C7/1006 ,  G11C11/4076 ,  G11C11/4096

摘要： A semiconductor memory device includes a memory cell array and an input/output path circuit. The input/output path circuit performs an input/output line pre-charge operation at a write end time point and outputs data stored in the memory cell array when the semiconductor memory device is operated in a read mode.

摘要翻译： 半导体存储器件包括存储单元阵列和输入/输出路径电路。 输入/输出路径电路在写入结束时间点执行输入/输出线预充电操作，并且当半导体存储器件以读取模式操作时，输出存储在存储单元阵列中的数据。