公开(公告)号：US11886746B1

公开(公告)日：2024-01-30

申请号：US17710572

申请日：2022-03-31

Applicant: DreamBig Semiconductor Inc.

Inventor： Sohail A Syed ,  Hillel Gazit ,  Hon Luu ,  Pranab Ghosh

IPC: G06F3/06 ,  G11C15/04 ,  G06F16/903 ,  G06F11/10

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0634 ,  G06F3/0679 ,  G06F16/90339 ,  G11C15/04 ,  G06F11/1064

Abstract: A method is provided to control a content addressable memory that includes multiple integrated circuit memory devices that include common memory address locations and that are coupled for simultaneous access to the common memory address locations, the method comprising; determining a hash value, based upon a received key value, that corresponds to a common memory address location of the multiple memory devices; providing activity status information for multiple common memory address locations of the memory devices; selecting a memory devices from which to output stored content data from the corresponding common memory address location, based upon storage activity status information; and causing the selected one or more memory devices to output stored content data.

公开(公告)号：US11922032B1

公开(公告)日：2024-03-05

申请号：US17710798

申请日：2022-03-31

Applicant: DreamBig Semiconductor Inc.

Inventor： Sohail A Syed ,  Hillel Gazit ,  Hon Luu ,  Pranab Ghosh

IPC: G06F3/06

CPC classification number: G06F3/0622 ,  G06F3/0656 ,  G06F3/0673

Abstract: A content addressable memory circuit is provided that includes: multiple integrated circuit memory devices that include memory address locations that share common memory addresses; buffer circuits operatively coupled to the memory devices; a hash table that includes a plurality of hash values that each corresponds to one or more key values; one or more processor circuits configured with instructions to perform operations that include: assigning each hash value to a memory address location based upon a first portion of the hash value; storing each key value at a memory address location assigned to a first portion of a hash value that corresponds to the key value; copying a first key value from a first memory address location within a memory device to a buffer circuit operatively coupled to the memory device; copying the first key value from the buffer circuit operatively coupled to the memory device to a second memory address location of the memory device; and assigning a second portion of a hash value that corresponds to the first key value to the second memory address location of the memory device.

公开(公告)号：US11683039B1

公开(公告)日：2023-06-20

申请号：US17710891

申请日：2022-03-31

Applicant: DreamBig Semiconductor Inc.

Inventor： Sohail A Syed ,  Hillel Gazit ,  Hon Luu ,  Pranab Ghosh

IPC: H03K19/1776 ,  G11C15/04 ,  H03K19/20 ,  H03K5/24

CPC classification number: H03K19/1776 ,  G11C15/04 ,  H03K5/2472 ,  H03K19/20

Abstract: A NOT logic circuit is provided comprising: one or more memory devices; wherein a first memory address location of the one or more memory devices stores first content data, wherein the first content data includes a first ternary value and a corresponding first priority value, wherein the first ternary value includes a continuous sequence of X-state values that represent a first range of non-X ternary values; wherein a second memory address of the one or more memory device stores second content data that includes a second ternary value and a corresponding second priority value, wherein the second ternary value includes a continuous sequence of non-X state values represent a non-X ternary value that is within the first range of non-X ternary values; an interface is coupled to receive a ternary value from a processing device; comparator circuitry operable to compare a received ternary key with the outputted first ternary value and to compare the received ternary key with the outputted second ternary value; priority encoder logic operable to, return the outputted first priority value on a condition that the received ternary key matches the first ternary value and the received ternary key does not match second ternary value, and return the outputted second priority value on a condition that the received ternary key matches the first ternary value and that the received ternary key matches the second ternary value; and detection logic operable to send a return to the processing device on a condition of a return of the first priority value.

公开(公告)号：US11899985B1

公开(公告)日：2024-02-13

申请号：US17710840

申请日：2022-03-31

Applicant: DreamBig Semiconductor Inc.

Inventor： Sohail A Syed ,  Hillel Gazit ,  Hon Luu ,  Pranab Ghosh

IPC: G06F3/06 ,  G06F9/455

CPC classification number: G06F3/0664 ,  G06F3/0604 ,  G06F3/0673 ,  G06F9/45558 ,  G06F2009/45583

Abstract: A content addressable memory circuit comprising: a memory device array including multiple memory devices coupled for simultaneous access to memory address locations that share a common memory address; multiple virtual modules (VMs), wherein each VM stores a data set that includes key values stored within an assigned memory address range within the memory array that are assigned to the VM; wherein each VM, stores a virtual hash table in non-transitory memory, that associates hash values with memory addresses within an assigned memory address range of the VM; hash logic is operable to determine a hash value, based upon a received key value and a respective assigned memory address range; and memory controller logic is operable to use a virtual hash table to access a memory address in an assigned memory address range, based upon the determined hash value.

公开(公告)号：US12184544B1

公开(公告)日：2024-12-31

申请号：US17710629

申请日：2022-03-31

Applicant: DreamBig Semiconductor Inc.

Inventor： Sohail A Syed ,  Hillel Gazit ,  Hon Luu ,  Pranab Ghosh

IPC: H04L45/745 ,  G11C8/08 ,  G11C15/04 ,  H04L9/40 ,  H04L45/42 ,  H04L45/586

Abstract: a content addressable memory circuit is provided that includes a memory array that includes multiple memory devices that include memory locations that share a memory address and are coupled for simultaneous access. Hash logic is operative to use modulo math to determine a memory address based upon non-X values within an IP address key. Memory controller logic is operative to cause a memory device in the memory array to store the received IP address key in a memory location at the determined memory address, in a format that includes a field-size value indicative of a number of non-X values within a received IP address key and that includes non-X values within the received IP address key.

公开(公告)号：US11720492B1

公开(公告)日：2023-08-08

申请号：US17710678

申请日：2022-03-31

Applicant: DreamBig Semiconductor Inc.

Inventor： Sohail A Syed ,  Hillel Gazit ,  Hon Luu ,  Pranab Ghosh

IPC: G06F12/06

CPC classification number: G06F12/0646 ,  G06F2212/251 ,  G06F2212/401

Abstract: A ternary content addressable memory is provided comprising; a memory device that includes a plurality of memory address locations; hash logic operative to determine a hash value, based upon a ternary key, wherein the determined hash value corresponds to a memory address location of the memory device; an encoder operable to convert the ternary key to a binary bit representation; wherein converting includes determining binary mapping bits based upon number and positions of ternary non-X (don't care) value bits of the ternary key; wherein converting further includes determining a different binary data bit to correspond to each different ternary non-X value bit of the ternary key; and memory controller logic to cause the memory device to store the binary bit representation at the memory address location that corresponds to the determined hash value.