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1.发明授权公开(公告)号：US07693088B2
公开(公告)日：2010-04-06
申请号：US11686144
申请日：2007-03-14
CPC分类号： H04L25/0262
摘要： Methods and apparatus are provided for data rate detection using a data eye monitor. The data rate is one of a plurality of data rates comprising a base rate and one or more divide-by-N multiples of the base rate, where N is an integer. The data rate of a received signal is detected by sampling the received signal; comparing the samples for a plurality of full rate data eyes associated with the received signal to determine if there is a mismatch between at least two predefined samples; and detecting the data rate by evaluating the comparison based on predefined criteria. The comparison can be performed by an exclusive or (XOR) logic gate for samples of at least two adjacent data eyes of a given rate.
摘要翻译： 提供了使用数据眼监视器进行数据速率检测的方法和装置。 数据速率是包括基本速率和基本速率的一个或多个除以N倍数的多个数据速率之一，其中N是整数。 通过对接收到的信号进行采样来检测接收信号的数据速率; 比较与所接收的信号相关联的多个全速率数据眼睛的样本，以确定是否存在至少两个预定样本之间的不匹配; 以及通过基于预定标准评估比较来检测数据速率。 可以通过异或（XOR）逻辑门对给定速率的至少两个相邻数据眼的样本执行比较。
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2.发明申请公开(公告)号：US20080225734A1
公开(公告)日：2008-09-18
申请号：US11686144
申请日：2007-03-14
IPC分类号： H04J1/16
CPC分类号： H04L25/0262
摘要： Methods and apparatus are provided for data rate detection using a data eye monitor. The data rate is one of a plurality of data rates comprising a base rate and one or more divide-by-N multiples of the base rate, where N is an integer. The data rate of a received signal is detected by sampling the received signal; comparing the samples for a plurality of full rate data eyes associated with the received signal to determine if there is a mismatch between at least two predefined samples; and detecting the data rate by evaluating the comparison based on predefined criteria. The comparison can be performed by an exclusive or (XOR) logic gate for samples of at least two adjacent data eyes of a given rate.
摘要翻译： 提供了使用数据眼监视器进行数据速率检测的方法和装置。 数据速率是包括基本速率和基本速率的一个或多个除以N倍数的多个数据速率之一，其中N是整数。 通过对接收到的信号进行采样来检测接收信号的数据速率; 比较与所接收的信号相关联的多个全速率数据眼睛的样本，以确定是否存在至少两个预定样本之间的不匹配; 以及通过基于预定标准评估比较来检测数据速率。 可以通过异或（XOR）逻辑门对给定速率的至少两个相邻数据眼的样本执行比较。
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3.发明授权Methods and apparatus for improved jitter tolerance in an SFP limit amplified signal 失效用于改善SFP限幅放大信号中抖动容限的方法和装置公开(公告)号：US08040984B2
公开(公告)日：2011-10-18
申请号：US11967602
申请日：2007-12-31
申请人： Pervez M. Aziz , Adam B. Healey , Mohammad S. Mobin , Gary E. Schiessler , Gregory W. Sheets , Lane A. Smith , Paul H. Tracy , Geoffrey Zhang
发明人： Pervez M. Aziz , Adam B. Healey , Mohammad S. Mobin , Gary E. Schiessler , Gregory W. Sheets , Lane A. Smith , Paul H. Tracy , Geoffrey Zhang
CPC分类号： H04B10/6972
摘要： Methods and apparatus are provided for improving the jitter tolerance in an SFP limit amplified signal. Jitter tolerance is improved in a communications receiver by applying a received signal to an SFP limiting amplifier; and applying an output of the SFP limiting amplifier to a low pass filter to improve the jitter tolerance. The low pass filter optionally applies a programmable amount of attenuation to high frequency components of the output. The low pass filter slew rate controls (i.e., rotates) a data eye representation of the received signal to increase the data eye representation along a time axis. The noise margin of the received signal can optionally be improved by applying an output of the low pass filter to an all pass filter. A slew rate controller can evaluate the data eye statistics to determine a setting for the low pass filter.
摘要翻译： 提供了用于改善SFP限幅放大信号中的抖动容限的方法和装置。 在通信接收机中通过将接收到的信号施加到SFP限幅放大器来提高抖动容差; 并将SFP限幅放大器的输出施加到低通滤波器以提高抖动容限。 低通滤波器可选择地将可编程量的衰减应用于输出的高频分量。 低通滤波器转换速率控制（即旋转）接收信号的数据眼表示，以沿着时间轴增加数据眼睛表示。 可以通过将低通滤波器的输出施加到全通滤波器来可选地改善接收信号的噪声容限。 压摆率控制器可以评估数据眼统计量，以确定低通滤波器的设置。
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公开(公告)号：US07765078B2
公开(公告)日：2010-07-27
申请号：US11967619
申请日：2007-12-31
IPC分类号： H03L7/06
CPC分类号： H03L7/0812
摘要： Methods and apparatus are provided for improved startup of a voltage controlled delay loop that has an injection clock and a return clock. A control signal is determined for a plurality of delay elements in a voltage controlled delay loop by obtaining a histogram count of a number of occurrences of at least one predefined logic value for a plurality of delay settings of the voltage controlled delay loop; determining a histogram count that approximately corresponds to an alignment of at least one edge in the injection and return clocks; and determining the control signal based on the determined histogram count that approximately corresponds to the alignment. The voltage controlled delay loop can be started using the determined control signal. The histogram count can be obtained for a plurality of PVT combinations and the control signal can then be determined for each PVT combination.
摘要翻译： 提供了用于改进启动具有注入时钟和返回时钟的电压控制延迟回路的方法和装置。 通过获得针对电压控制的延迟环路的多个延迟设置的至少一个预定逻辑值的出现次数的直方图计数，为电压控制的延迟环路中的多个延迟元件确定控制信号; 确定近似对应于所述注入和返回时钟中的至少一个边缘的对准的直方图计数; 以及基于大致对应于所述对准的所确定的直方图计数来确定所述控制信号。 可以使用所确定的控制信号来开始压控延迟环路。 可以为多个PVT组合获得直方图计数，然后可以为每个PVT组合确定控制信号。
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公开(公告)号：US20090167379A1
公开(公告)日：2009-07-02
申请号：US11967619
申请日：2007-12-31
IPC分类号： H03L7/06
CPC分类号： H03L7/0812
摘要： Methods and apparatus are provided fox improved startup of a voltage controlled delay loop that has an injection clock and a return clock. A control signal is determined for a plurality of delay elements in a voltage controlled delay loop by obtaining a histogram count of a number of occurrences of at least one predefined logic value for a plurality of delay settings of the voltage controlled delay loop; determining a histogram count that approximately corresponds to an alignment of at least one edge in the injection and return clocks; and determining the control signal based on the determined histogram count that approximately corresponds to the alignment. The control signal can be, for example, a delay control current or a delay control voltage. The voltage controlled delay loop can be started using the determined control signal. The histogram count can be obtained for a plurality of PVT combinations and the control signal can then be determined for each PVT combination. The determined control signal can optionally be stored in a table for each of the plurality of PVT combinations
摘要翻译： 提供了具有注入时钟和返回时钟的电压控制延迟回路的改进的启动方法和装置。 通过获得针对电压控制的延迟环路的多个延迟设置的至少一个预定逻辑值的出现次数的直方图计数，为电压控制的延迟环路中的多个延迟元件确定控制信号; 确定近似对应于所述注入和返回时钟中的至少一个边缘的对准的直方图计数; 以及基于大致对应于所述对准的所确定的直方图计数来确定所述控制信号。 控制信号可以是例如延迟控制电流或延迟控制电压。 可以使用所确定的控制信号来开始压控延迟环路。 可以为多个PVT组合获得直方图计数，然后可以为每个PVT组合确定控制信号。 所确定的控制信号可以可选地存储在用于多个PVT组合中的每一个的表中
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公开(公告)号：US08432959B2
公开(公告)日：2013-04-30
申请号：US11930814
申请日：2007-10-31
CPC分类号： H04L25/0262 , H04L25/03006 , H04L25/03057 , H04L2025/03375 , H04L2025/03535 , H04L2025/03726
摘要： Methods and apparatus are provided for equalizing a received signal. A received signal is equalized by updating one or more equalization parameters; and discarding the updated equalization parameters if one or more predefined qualifier conditions are detected during the equalizing step. The received signal can optionally be equalized using the updated equalization parameters if the predefined qualifier conditions are not detected during the equalizing step. The updated equalization parameters can optionally be stored if the one or more predefined qualifier conditions are not detected during the equalizing step.
摘要翻译： 提供了用于均衡接收信号的方法和装置。 通过更新一个或多个均衡参数来使接收信号相等; 以及如果在均衡步骤期间检测到一个或多个预定义的限定条件，则丢弃所述更新的均衡参数。 如果在平衡步骤期间未检测到预定义的限定条件，则可以使用更新的均衡参数来选择性地均衡所接收的信号。 如果在均衡步骤期间未检测到一个或多个预定义限定条件，则可以可选地存储更新的均衡参数。
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7.发明申请Methods and Apparatus for Detecting a Loss of Lock Condition in a Clock and Data Recovery System 有权用于检测时钟和数据恢复系统中锁定状态丢失的方法和装置公开(公告)号：US20090168936A1
公开(公告)日：2009-07-02
申请号：US11967632
申请日：2007-12-31
IPC分类号： H04L7/00
CPC分类号： H04L7/0062 , H04L7/0083
摘要： Methods and apparatus are provided for detecting a loss of lock condition in a clock and data recovery system. A loss of lock condition is detected in a clock and data recovery system that generates a recovered clock signal from a received signal by sampling the received signal for a plurality of different phases using one or more latches clocked by the recovered clock; evaluating the samples to monitor a data eye associated with the received signal; and detecting the loss of lock condition if the data eye does not satisfy one or more predefined conditions. Generally, the predefined conditions identify a loss of the data eye (e.g, when the data eye cannot be substantially detected), for example, based on a degree of opening of the data eye. The clock and data recovery system can optionally be restarted if the loss of lock condition is detected.
摘要翻译： 提供了用于检测时钟和数据恢复系统中的锁定状况的损失的方法和装置。 在时钟和数据恢复系统中检测到锁定状态的损失，该系统通过使用由恢复时钟计时的一个或多个锁存器对接收到的信号进行多个不同相位的采样来产生来自接收信号的恢复时钟信号; 评估样本以监测与接收信号相关联的数据眼; 并且如果数据眼不满足一个或多个预定条件，则检测锁定条件的损失。 通常，预定条件识别数据眼的损失（例如，当数据眼不能被基本上被检测时），例如，基于数据眼的打开程度。 如果检测到锁定状态的丢失，则可以可选地重新启动时钟和数据恢复系统。
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公开(公告)号：US20090110046A1
公开(公告)日：2009-04-30
申请号：US11930814
申请日：2007-10-31
IPC分类号： H03K5/159
CPC分类号： H04L25/0262 , H04L25/03006 , H04L25/03057 , H04L2025/03375 , H04L2025/03535 , H04L2025/03726
摘要： Methods and apparatus are provided for equalizing a received signal. A received signal is equalized by updating one or more equalization parameters; and discarding the updated equalization parameters if one or more predefined qualifier conditions are detected during the equalizing step. The received signal can optionally be equalized using the updated equalization parameters if the predefined qualifier conditions are not detected during the equalizing step. The updated equalization parameters can optionally be stored if the one or more predefined qualifier conditions are not detected during the equalizing step
摘要翻译： 提供了用于均衡接收信号的方法和装置。 通过更新一个或多个均衡参数来使接收信号相等; 以及如果在均衡步骤期间检测到一个或多个预定义的限定条件，则丢弃所述更新的均衡参数。 如果在平衡步骤期间未检测到预定义的限定条件，则可以使用更新的均衡参数来选择性地均衡所接收的信号。 如果在均衡步骤期间未检测到一个或多个预定义限定条件，则可以可选地存储更新的均衡参数
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9.发明申请Method and apparatus for non-linear decision-feedback equalization in the presence of asymmetric channel 有权在存在非对称信道的情况下进行非线性判决反馈均衡的方法和装置公开(公告)号：US20080080609A1
公开(公告)日：2008-04-03
申请号：US11541379
申请日：2006-09-29
IPC分类号： H03H7/30
CPC分类号： H04L25/03057 , H04B10/695
摘要： Methods and apparatus are provided for determining the threshold position of one or more latches employed for decision-feedback equalization in the presence of a non-linear channel. A latch employed by a decision-feedback equalizer is positioned by constraining input data such that the input data only contains transitions from a first binary value; obtaining a plurality of samples of a single-sided data eye associated with the constrained input data; determining a threshold position of the latch based on the samples; and transforming the determined position to address the non-linearity of the channel. For example, a non-linear mapping table can map measured threshold values to transformed threshold values based on distance.
摘要翻译： 提供了用于在存在非线性通道的情况下确定用于判决反馈均衡的一个或多个锁存器的阈值位置的方法和装置。 由判决反馈均衡器采用的锁存器通过约束输入数据来定位，使得输入数据仅包含来自第一二进制值的转换; 获得与所述约束输入数据相关联的单面数据眼睛的多个样本; 基于所述样本确定所述锁存器的阈值位置; 并且变换确定的位置以解决信道的非线性。 例如，非线性映射表可以将测量的阈值映射到基于距离的变换的阈值。
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公开(公告)号：US08219344B2
公开(公告)日：2012-07-10
申请号：US12789544
申请日：2010-05-28
IPC分类号： H03L7/06
CPC分类号： H03L7/0812
摘要： Methods and apparatus are provided for improved startup of a voltage controlled delay loop that has an injection clock and a return clock. A control signal is determined for a plurality of delay elements in a voltage controlled delay loop by obtaining a histogram count of a number of occurrences of at least one predefined logic value for a plurality of delay settings of the voltage controlled delay loop; determining a histogram count that approximately corresponds to an alignment of at least one edge in the injection and return clocks; and determining the control signal based on the determined histogram count that approximately corresponds to the alignment. The voltage controlled delay loop can be started using the determined control signal. The histogram count can be obtained for a plurality of PVT combinations and the control signal can then be determined for each PVT combination.
摘要翻译： 提供了用于改进启动具有注入时钟和返回时钟的电压控制延迟回路的方法和装置。 通过获得针对电压控制的延迟环路的多个延迟设置的至少一个预定逻辑值的出现次数的直方图计数，为电压控制的延迟环路中的多个延迟元件确定控制信号; 确定近似对应于所述注入和返回时钟中的至少一个边缘的对准的直方图计数; 以及基于大致对应于所述对准的所确定的直方图计数来确定所述控制信号。 可以使用所确定的控制信号来开始压控延迟环路。 可以为多个PVT组合获得直方图计数，然后可以为每个PVT组合确定控制信号。
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