公开(公告)号：US20220180162A1

公开(公告)日：2022-06-09

申请号：US17544224

申请日：2021-12-07

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Jin-Ho HAN ,  Young-Su KWON ,  Mi-Young LEE ,  Joo-Hyun LEE ,  Yong-Cheol CHO

IPC: G06N3/063

Abstract: Disclosed herein is an AI accelerator. The AI accelerator includes processors, each performing a deep-learning operation using multiple threads; and a cache memory including an L0 instruction cache for providing instructions to the processors and an L1 cache mapped to the multiple areas of mapped memory.

公开(公告)号：US20220171708A1

公开(公告)日：2022-06-02

申请号：US17536573

申请日：2021-11-29

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Joo-Hyun LEE ,  Young-Su KWON ,  Jin-Ho HAN

IPC: G06F12/084 ,  G06F8/41 ,  G06F8/60

Abstract: Disclosed herein is a heterogeneous system based on unified virtual memory. The heterogeneous system based on unified virtual memory may include a host for compiling a kernel program, which is source code of a user application, in a binary form and delivering the compiled kernel program to a heterogenous system architecture device, the heterogenous system architecture device for processing operation of the kernel program delivered from the host in parallel using two or more different types of processing elements, and unified virtual memory shared between the host and the heterogenous system architecture device.

公开(公告)号：US20240202277A1

公开(公告)日：2024-06-20

申请号：US18538145

申请日：2023-12-13

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Joo-Hyun LEE

IPC: G06F17/16 ,  G06F7/544

CPC classification number: G06F17/16 ,  G06F7/5443

Abstract: Disclosed herein is an apparatus and method for a matrix multiplication operation. The apparatus may include memory for storing first matrix data and second matrix data, an X buffer for storing the first matrix data, a Y buffer for storing the second matrix data, multiple operation units for performing Multiply-and-Accumulate (MAC) operations in parallel on the data input from the X buffer and the Y buffer, and a data loader for storing the first matrix data and the second matrix data read from the memory in the X buffer and the Y buffer, respectively.

公开(公告)号：US20240062809A1

公开(公告)日：2024-02-22

申请号：US18499634

申请日：2023-11-01

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Jin-Ho HAN ,  Byung-Jo KIM ,  Ju-Yeob KIM ,  Hye-Ji KIM ,  Joo-Hyun LEE ,  Seong-Min KIM

IPC: G11C11/4096 ,  G06F7/544 ,  G06N3/063 ,  G11C11/4093 ,  G11C11/54

CPC classification number: G11C11/4096 ,  G06F7/5443 ,  G06N3/063 ,  G11C11/4093 ,  G11C11/54

Abstract: Disclosed herein is an Artificial Intelligence (AI) processor. The AI processor includes multiple NVM AI cores for respectively performing basic unit operations required for a deep-learning operation based on data stored in NVM; SRAM for storing at least some of the results of the basic unit operations; and an AI core for performing an accumulation operation on the results of the basic unit operation.

公开(公告)号：US20230130429A1

公开(公告)日：2023-04-27

申请号：US17972116

申请日：2022-10-24

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Joo-Hyun LEE

IPC: G06F11/36 ,  G06F11/07

Abstract: Disclosed herein are a method for debugging a program of many core parallel processors based on code execution and an apparatus for the same. The method, performed by debugger software running on a host processor, includes generating a program execution binary including debug execution code and providing the same to multiple parallel processors, acquiring context data corresponding to the state of a target processor immediately before the debug execution code is executed in the target processor, among the multiple parallel processors, and analyzing the context data and thereby performing debugging of a program executed in the processor in which the debug execution code is executed.